Verilog: the other HDL

Describing hardware in a C-like language

4 min read

Verilog is a hardware description language (HDL) that, like VHDL, describes digital hardware as text so it can be simulated and synthesised into real gates; its unit of design is the module (a named block with an input/output port list), and its C-like syntax makes it the most common HDL in US chip design.

Builds onWhat is an HDL?Designing gates from truth tables

You met VHDL, one way to describe hardware as text. Verilog is the other. Both are IEEE-standard HDLs that a synthesis tool turns into the same gates you build on the canvas; the difference is dialect. VHDL reads like Ada: verbose, strongly typed, strict. Verilog reads like C: terse, case-sensitive, quick to write. Most US universities and most commercial chip (ASIC) design lean Verilog; European and defense work leans VHDL. Learn to read both and no HDL codebase is foreign.

The module: Verilog's building block

Where VHDL splits a design into an entity (the interface) and an architecture (the guts), Verilog folds both into one module. A module has a name, a port list (its inputs and outputs, the pins), and a body that describes the logic. module ... endmodule wraps the whole thing, just as entity/architecture did. A port is input, output, or inout (bidirectional, for a shared bus). Here is a two-input AND gate:

module and_gate(
  input  A,
  input  B,
  output F
);
  assign F = A & B;
endmodule

A Verilog module for an AND gate. The port list names the pins (two inputs, one output); the single assign line is the logic. Compare it to the VHDL entity/architecture: same circuit, fewer words.

Read it as the diagram it is: a box named and_gate with pins A, B, and F, and inside, one AND gate (&) driving F from A and B. The port list is the box's boundary, the INPUT and PROBE markers you place on the canvas; the assign line is the wire-and-gate inside. That is the whole idea: a module is a labelled circuit block.

Two Verilog habits that trip up VHDL users: Verilog is case-sensitive, so clk and CLK are different names, and every statement ends with a semicolon ;. Comments are C-style: // to end of line, or /* ... */. Miss a semicolon or mismatch a name's case and the tool complains, so stay consistent from the start.

Why this matters: Verilog and VHDL describe the *same* hardware, so everything you learned building circuits, gates, adders, registers, a CPU, maps to both. The next two lessons show the two core styles in Verilog: assign for combinational logic (a standing gate network) and always @(posedge clk) for sequential logic (memory), the exact pair you met as concurrent assignments and processes in VHDL.

Try it

In the AND-gate module, which line is the *interface* (the box's pins) and which is the *logic* (what is inside)? And what would you change to make it a two-input OR gate?

Frequently asked

What is Verilog?

Verilog is a hardware description language (HDL): a text language for describing digital circuits so they can be simulated and synthesised into real gates. It has a C-like syntax and is the most widely used HDL in US chip (ASIC) design.

What is the difference between Verilog and VHDL?

Both are IEEE-standard HDLs that synthesise to the same hardware. Verilog is terser and C-like (case-sensitive, semicolons), popular in US industry and ASIC design; VHDL is more verbose and strongly typed (Ada-like), popular in Europe and defense work. Learning one makes the other easy to read.

What is a module in Verilog?

A module is Verilog's basic design block: a named unit with a port list (its input/output pins) and a body describing the logic, all wrapped in module ... endmodule. It is the equivalent of a VHDL entity plus architecture combined, and it corresponds to one labelled circuit block.

Is Verilog case-sensitive?

Yes. In Verilog, clk and CLK are two different names, unlike VHDL which is case-insensitive. Every statement also ends in a semicolon, and comments use C-style // or /* */.

Every lesson here builds toward one thing: a working CPU, from the transistor up.

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