Transistor count and sizing
How many transistors, and how wide
A static CMOS gate uses two transistors per input (one NMOS, one PMOS), and because a transistor's drive current grows with its width, designers make PMOS pull-ups wider than NMOS pull-downs and widen transistors stacked in series so the gate switches at a balanced, predictable speed.
You can now build any gate from transistors. Two practical questions decide whether that gate is any good in a real chip: how many transistors does it take, and how big should each one be? Neither changes the logic (a wide transistor and a narrow one switch on the same input), but both decide speed, area, and power. This lesson gives the intuition, not the equations.
Counting transistors
Static CMOS has a simple rule of thumb: two transistors per input (one NMOS in the pull-down, one PMOS in the pull-up). So the natural inverting gates cost:
- NOT: 1 input, 2 transistors.
- NAND / NOR (2-input): 2 inputs, 4 transistors. An n-input NAND or NOR is
2ntransistors. - AND / OR (2-input): a NAND or NOR (4) plus an inverter (2), 6 transistors, because the non-inverting gates need a stage to cancel the natural inversion (see AND and OR).
- XOR (2-input): about 8 transistors with transmission gates, or more if built from four NANDs. It is the priciest of the small gates, which is why adders are counted carefully.
Transistor count is why chip designers care so much about logic minimization (Karnaugh maps) and about building from NAND and NOR: every product term and every stray inverter you can remove is transistors, area, and power saved, multiplied across the billions of gates on a modern die.
Sizing: width sets drive strength
A transistor's job when it turns on is to move charge onto or off of the wire it drives (recall from why CMOS sips power that every wire is a little capacitor). How fast it can do that, its drive strength, is set mainly by how wide the transistor is. A wider transistor is a fatter pipe: it passes more current, so it charges the load faster and switches sooner. Making a transistor wider costs area and adds its own capacitance, so sizing is a balancing act, not a free win.
Balancing rise and fall: the wider PMOS
Recall from the PMOS lesson that holes move more slowly than electrons, so a PMOS of the same width as an NMOS drives *weaker*. If you built an inverter with equal-width transistors, it would pull down (through the fast NMOS) quicker than it pulls up (through the slow PMOS): a lopsided gate with a rising edge slower than its falling edge. To even them out, the PMOS is made wider than the NMOS, typically around twice as wide, so the pull-up and pull-down drive equally and the gate's rise and fall times match.
Sizing up series stacks
Transistors in series stack their resistances: two in series conduct about half as hard as one alone, three about a third as hard, and so on. That directly slows the network they are in. To claw the speed back, series-stacked transistors are made wider in proportion to how many are stacked. In a 2-input NAND, the two series NMOS are each widened (roughly doubled) so the series pair drives about as hard as a single reference NMOS.
The two effects compound and explain a practical preference. A NAND stacks NMOS (already fast) in series, so it needs only modest widening. A NOR stacks PMOS (already the slow, wide device) in series, so its transistors must be widened a lot to keep up, making a NOR bigger and slower than a NAND. That is a big reason designers reach for NAND first.
Sizing is a trade-off, not "bigger is better." A wider transistor drives its load faster but presents a bigger capacitive load to whatever gate drives *it*, so oversizing one gate just pushes the delay upstream and burns more switching power. Real designs size a gate to the load it must drive: small gates for light local loads, progressively larger buffers to drive a heavy wire or high fan-out. Blindly widening everything makes a chip slower and hotter, not faster.
Check yourself
You build an inverter with the NMOS and PMOS the same width. Which edge is slower, rising or falling, and how do you fix it? Then: why does a 2-input NOR usually end up larger than a 2-input NAND?
Answer
Build it in the lab ↗The rising edge is slower, because it is driven by the weaker PMOS (slow holes) while the falling edge uses the faster NMOS. Fix it by making the PMOS wider (about 2x) so pull-up and pull-down drive equally. A NOR is larger because its series stack is made of PMOS: the already-wide slow device, now stacked in series, must be widened a lot to keep speed, whereas a NAND stacks the fast NMOS and needs less widening.
Frequently asked
How many transistors are in a logic gate?
In static CMOS, about two transistors per input: an inverter is 2, a 2-input NAND or NOR is 4 (an n-input one is 2n), a 2-input AND or OR is 6 (a NAND/NOR plus an inverter), and a 2-input XOR is around 8. The non-inverting gates cost extra because they need a stage to cancel the natural inversion.
Why is a PMOS made wider than an NMOS in a gate?
Because a PMOS conducts using holes, which move more slowly than the electrons in an NMOS, so an equal-width PMOS drives weaker. Making the PMOS about twice as wide balances the pull-up and pull-down strengths so the gate's rising and falling edges take equal time.
Why are series-stacked transistors sized wider?
Because transistors in series add their resistances, so a stack of them drives more weakly and switches slower than a single transistor. Widening each stacked transistor in proportion to the stack height restores the drive strength and keeps the gate fast.
Why do designers prefer NAND over NOR in CMOS?
A NAND stacks fast NMOS in series and needs only modest widening, while a NOR stacks the slower, already-wide PMOS in series and must be widened much more to match. So a NOR ends up larger and slower, making NAND the more efficient default building block.
You have built every gate, counted its transistors, and sized them. One step remains: from transistors to gate symbols, where we agree to stop drawing switches and start drawing gates.
Every lesson here builds toward one thing: a working CPU, from the transistor up.
Open the free lab →