The instruction register
Holding and splitting an instruction
The instruction register latches the instruction byte fetched from memory and holds it steady while the CPU acts on it, exposing it split into an opcode (what to do) and an operand (what to do it to).
When the CPU fetches an instruction, the byte comes off the memory bus for just an instant. The machine then needs to *act* on that instruction over several steps, and the bus will be busy carrying other values in the meantime. So the fetched byte has to be held. That is the job of the instruction register (IR): an 8-bit register that latches the instruction and keeps it stable while the rest of the CPU reads it.
An instruction is an opcode plus an operand
An instruction byte is split into two fields. The high bits are the opcode: a number naming *what to do* (load, add, store, jump). The low bits are the operand: usually *what to do it to*, most often a memory address. In our small machine the byte splits down the middle: the high 4 bits
I4-I7 are the opcode, and the low 4 bits I0-I3 are the operand. Four opcode bits give up to sixteen different instructions; four operand bits address sixteen memory locations.instruction = opcode (high 4 bits) , operand (low 4 bits)
The split is nothing but wiring. The register stores all 8 bits as one byte; we simply route the top 4 output bits to the opcode lines and the bottom 4 to the operand lines. No gates, no logic, just naming which wires are which. The opcode wires then feed the control unit, and the operand wires feed the address bus.
Latch once, read all step
During the fetch step, the control logic raises the IR's load line for one clock edge, capturing the instruction byte off the bus. After that the load line drops, so the IR holds that instruction unchanged for the rest of the cycle while the opcode and operand stay valid. Every later step of executing the instruction reads these stable outputs.
IR8): load a byte on I0-I7 with LD, and read it back split into opcode OP0-OP3 (high nibble) and operand AR0-AR3 (low nibble). Before a load the outputs read Z; open it in the lab, set a byte like 1011 0111, pulse LD, and read opcode 1011 and operand 0111.Try it
Load the byte
0010 1110 (which is 0x2E) into the IR. What appears on the opcode lines OP0-OP3 and the operand lines AR0-AR3? What instruction is this, given opcode 0x2 is ADD?Answer
The high nibble
0010 (0x2) goes to OP0-OP3; the low nibble 1110 (0xE = 14) goes to AR0-AR3. So opcode 0x2 (ADD) on address 14: the instruction ADD 14. The split is pure wiring, no logic, exactly the inverse of assembling the byte in the machine code lesson.Now the CPU is holding an instruction it can read as 'operation X on address Y'. Two things happen next: the machine code lesson nails down which opcodes mean what (the instruction set), and the control unit looks at the opcode and pulls the right levers, in the right order, to carry it out: load the operand's address, read memory, run the ALU, store the result.
Frequently asked
What is an instruction register?
An instruction register (IR) is an 8-bit register that latches the instruction byte fetched from memory and holds it steady while the CPU acts on it. It exposes that byte split into an opcode (what to do) and an operand (what to do it to), so the control unit can decode the opcode while the bus moves other values.
Why does the CPU need an instruction register at all?
The fetched byte is on the memory bus for only an instant, and executing an instruction takes several steps during which the bus is busy carrying other values. The IR holds the instruction stable across those steps so its opcode and operand stay valid the whole time.
How does the instruction register split an instruction into opcode and operand?
Purely by wiring: the IR stores all 8 bits as one byte, then the top 4 output bits
I4-I7 are routed to the opcode lines and the bottom 4 bits I0-I3 to the operand lines. No gates, just naming which wires are which. Four opcode bits name up to 16 instructions; four operand bits address 16 locations.What is the difference between an instruction register and a program counter?
The instruction register holds the *current instruction's byte* (its opcode and operand) so it can be decoded. The program counter holds the *address of the next instruction* and increments each cycle. One says what to do now, the other says where to look next.
Every lesson here builds toward one thing: a working CPU, from the transistor up.
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