OR gate from transistors: CMOS NOR plus inverter, live

A CMOS OR gate takes six transistors: a four-transistor NOR gate followed by a two-transistor inverter. The NOR stage pulls an inner node X low as soon as A or B is 1, and the inverter turns that into Y = A OR B.

The first stage is the CMOS NOR gate: two PMOS in series from VDD to X, so X is pulled high only when A and B are both 0, and two NMOS in parallel from X to ground, so either input at 1 pulls X low. The second stage is a CMOS inverter that turns X = NOT (A OR B) into Y = A OR B. As with the CMOS AND gate, one stage cannot do it: a static CMOS stage pulls up through PMOS, which turn on when their inputs are 0, so every single stage inverts and a non-inverting gate costs an extra inverter. OR is the more expensive of the two in practice, because its NOR stage stacks PMOS, the weaker kind of transistor, in series, and they must be made wider to keep it fast. More in the pull-up and pull-down network lessons.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× PMOS transistor: NOR stage pull-up: in series from VDD to X, gated by A and by B
2× NMOS transistor: NOR stage pull-down: in parallel from X to GND, gated by A and by B
1× PMOS transistor: inverter pull-up from VDD to Y, gated by X
1× NMOS transistor: inverter pull-down from Y to GND, gated by X

Step by step

Place VDD, GND, inputs A and B, and a probe Y.
Build the NOR stage: two PMOS in a stack from VDD to a node X, gated by A and B, and two NMOS side by side from X to GND, one gated by A and one by B.
Build an inverter on X: a PMOS from VDD to Y and an NMOS from Y to GND, both gated by X.
Try all four input pairs: X is 1 only for A = B = 0, so Y is 0 only then.

CMOS OR truth table, stage by stage

A	B	NOR PMOS stack	NOR NMOS on	X (NOR)	Y (OR)
0	0	closed	none	1	0
0	1	open	B's	0	1
1	0	open	A's	0	1
1	1	open	both	0	1

Only the first row closes the whole PMOS stack; in the other three at least one NMOS pulls X to 0 and the inverter raises Y. All four rows are checked on the live circuit, which is made of transistors only, before the page is built.

You can also read the full theory in the lesson on the OR gate. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the CMOS OR gate in the lab →

Frequently asked

How many transistors are needed for an OR gate?

Six in CMOS: four for a NOR gate and two for the inverter after it. A 3-input OR needs eight: six for the 3-input NOR and two for the inverter.

Why can't CMOS make an OR gate in one stage?

In a static CMOS stage the PMOS pull-up conducts when its inputs are 0 and the NMOS pull-down when they are 1, so raising an input can only pull the output down. Every single stage inverts, so OR is built as NOR followed by NOT.

What is the difference between a CMOS NOR and an OR gate?

OR is NOR plus an inverter: 6 transistors instead of 4 and one more gate delay. Where they can, designers keep the inversion and restructure the logic around NOR or NAND instead.

Can you build an OR gate from diodes instead?

Yes, in diode logic: one diode from each input to the output and a resistor from the output to ground. It cannot restore weak signal levels or drive long chains of gates, which is why chips use CMOS.