How to build a 4-bit universal shift register from logic gates

A universal shift register can hold, shift right, shift left or load all its bits in parallel, chosen by two mode bits S1 S0 (00 hold, 01 shift right, 10 shift left, 11 load). Each stage is a D flip-flop fed by a 4-to-1 multiplexer that picks its next value.

It combines every kind of shift register in one circuit, which is why it is called universal: serial in or parallel in, serial out or parallel out, in either direction. The trick is that every stage has the same four candidates for its next value: itself (hold), its left neighbour (shift right), its right neighbour (shift left) or its own parallel input (load), and a 4-to-1 mux steered by S1 S0 chooses. This is the scheme of the classic 74194 chip. The live circuit opens in load mode with all parallel inputs at 0, so the running clock loads 0000 straight away; set your inputs and change the mode to shift.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

4× D flip-flop: the four stages Q0 to Q3, on one clock
2× NOT: NOT S1 and NOT S0
4× AND: decoding S1 S0 into four one-hot mode lines (shared by all stages)
16× AND: per stage, gating each candidate value with its mode line
12× OR: per stage, merging the four gated candidates (3 ORs each)

Step by step

Place a clock CLK, mode inputs S1, S0, serial inputs SR (shift right in) and SL (shift left in), parallel inputs I3 to I0, and four D flip-flops for Q0 to Q3.
Decode the mode into four lines: hold (S1' S0'), shift right (S1' S0), shift left (S1 S0'), load (S1 S0).
For each stage build a 4-to-1 mux: hold selects its own Q, shift right selects the stage to its left (SR for Q0), shift left selects the stage to its right (SL for Q3), load selects its parallel input I. Wire the mux into the flip-flop's D.
Probe Q0 to Q3. Load 1011 with mode 11, then switch to 01 and watch the pattern move toward Q3, or to 10 and watch it move toward Q0.

Mode table

S1	S0	Mode	Next Q0	Next Q1	Next Q2	Next Q3
0	0	hold	Q0	Q1	Q2	Q3
0	1	shift right	SR	Q0	Q1	Q2
1	0	shift left	Q1	Q2	Q3	SL
1	1	parallel load	I0	I1	I2	I3

Here Q0 is the first stage, so "shift right" moves data from Q0 toward Q3, the 74194's convention (its QA is the first stage). The verification loads a pattern, holds it, shifts it right twice and left twice with different serial inputs, then loads again, checking all four stages at every clock against a reference model.

You can also read the full theory in the lesson on shift registers. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 4-bit universal shift register in the lab →

Frequently asked

What is a universal shift register?

A shift register that can do all the basic operations: hold its data, shift right, shift left, and load all bits in parallel, selected by mode inputs. It can therefore act as SISO, SIPO, PISO or PIPO in either direction.

How does a universal shift register work?

Every stage is a flip-flop whose D input comes from a 4-to-1 multiplexer. The mux inputs are the stage's own output (hold), its neighbours' outputs (shift right or left, with serial inputs at the ends) and a parallel data input (load), and the mode bits S1 S0 drive the mux selects.

What is the difference between a bidirectional and a universal shift register?

A bidirectional shift register can shift left or right. A universal shift register also adds parallel load (and hold), so it supports every combination of serial and parallel input and output.

What is the 74194?

A 4-bit bidirectional universal shift register chip with mode inputs S1 S0 (hold, shift right, shift left, parallel load), serial inputs for each direction, and an asynchronous clear.