How to build a decade counter from logic gates

A decade counter counts 0 to 9 and then returns to 0, ten states per cycle, so its four outputs are always one BCD digit. This one is a synchronous 4-bit counter whose next state is forced to 0000 when the count reaches 9, with a terminal-count output TC that is 1 at 9.

A plain 4-bit counter has 16 states. To stop at ten, detect the last wanted state and make the next edge load zero instead of counting on. Because the counter only ever passes through 0 to 9, the state 9 (1001) is the only one with both Q3 and Q0 set, so a single AND gate Q3 AND Q0 detects it. That same signal is TC: wire it to the next decade's count enable and two decade counters count 00 to 99. The live clock is already running: pulse CLR for one tick, then watch it count 0 to 9 and roll over.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

4× D flip-flop: the four BCD bits, on one clock
3× XOR: next state of bits 1 to 3 (binary counting)
2× AND: the toggle chain Q1 Q0 and Q2 Q1 Q0
1× AND: TC = Q3 AND Q0, true only at 9
1× OR: reset when CLR or TC
4× AND: masking each D input with NOT (CLR OR TC)
2× NOT: NOT Q0 and the inverted reset

Step by step

Start from the 4-bit synchronous counter: D0 = NOT Q0, and bit k gets Q_k XOR (all lower bits are 1).
Detect nine: TC = Q3 AND Q0. No other state from 0 to 9 has both of those bits set.
Make the reset: OR TC with CLR and invert it.
AND every next-state signal with that inverted reset before it reaches a D input. At 9 the next edge therefore loads 0000 instead of 1010.
Probe Q0 to Q3 and TC. Pulse CLR, then watch 0000 up to 1001, TC light at 9, and the roll back to 0000.

Decade counter sequence

Clock edge	Q3 Q2 Q1 Q0	Digit	TC
CLR	0000	0	0
1	0001	1	0
2	0010	2	0
5	0101	5	0
8	1000	8	0
9	1001	9	1
10	0000	0	0

Ten states, then repeat: the pattern comes round every ten clocks, so Q3 and TC each pulse at a tenth of the clock frequency, which is why decade counters divide by ten in frequency counters and digital clocks. The codes 1010 to 1111 never appear after a clear. Feed Q3..Q0 into a BCD to 7-segment decoder and you have one digit of a counter display. The run checks all four bits and TC over 13 clocks, through the rollover.

You can also read the full theory in the lesson on counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the decade counter in the lab →

Frequently asked

What is a decade counter?

A counter with ten states, 0 to 9, that returns to 0 after 9. Its four outputs form a BCD digit, so it is also called a BCD or mod-10 counter.

How do you make a mod-10 counter from a 4-bit counter?

Detect the count where it must restart and force the next state to 0. Synchronously, detect 9 (Q3 AND Q0) and clear on the next clock edge, as here. Asynchronous designs instead detect 10 (Q3 AND Q1) and reset immediately, which briefly shows 1010 and can glitch.

Why is Q3 AND Q0 enough to detect 9?

In the states 0 to 9 only 9 (1001) has both Q3 and Q0 set; 8 is 1000 and 10 to 15 are never reached. A full 4-input decode is only needed when other states can occur.

What is the difference between a decade counter and a Johnson counter like the CD4017?

This decade counter counts in binary (BCD) on four flip-flops. The CD4017 also has ten states but is a 5-stage Johnson counter with ten decoded one-hot outputs, so exactly one of its outputs is high at a time.