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How to build an SR latch using NAND gates

An SR latch made from two cross-coupled NAND gates stores one bit with active-low inputs: pulling S-bar low sets Q to 1, pulling R-bar low resets Q to 0, and holding both high keeps the stored bit. Both low at once is the invalid case.

It is the NAND twin of the NOR SR latch. A NAND's output is forced to 1 whenever either input is 0, so here a 0 on an input is what takes control, which is why the inputs are written with a bar (S̄, R̄) and called active-low. With both inputs at 1 each NAND simply inverts the other's output, and the loop holds whichever state it is in. The live circuit starts with R-bar held low, so Q = 0: set R-bar to 1 to release it and the 0 stays; then pulse S-bar low to store a 1.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

Step by step

  1. Place inputs Sbar and Rbar and two NAND gates.
  2. Wire Sbar into the first NAND; its output is Q. Wire Rbar into the second NAND; its output is Qbar.
  3. Cross-couple them: Qbar into the first NAND's other input, Q into the second NAND's other input.
  4. Probe Q and Qbar. With both inputs at 1 the latch holds. Pull Sbar to 0: Q becomes 1. Return it to 1: Q stays 1. Pull Rbar to 0: Q becomes 0 and stays when Rbar returns to 1.

NAND SR latch truth table

SbarRbarQ (next)Action
11holdkeep the stored bit
011set
100reset
00invalidQ = Qbar = 1

Compare the NOR latch: there S = R = 0 holds and S = R = 1 is invalid. The NAND latch has the same behaviour with every input inverted, which is why it is often drawn with S̄ and R̄. Driving both inputs low forces both outputs to 1, breaking the rule that Qbar is the opposite of Q, and releasing them together leaves an unpredictable state. The verification steps through set, hold, reset, hold and set again with the simulator's memory carried between steps.

You can also read the full theory in the lesson on the SR latch. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the SR latch from NAND gates in the lab →

Frequently asked

How do you make an SR latch with NAND gates?

Cross-couple two NAND gates: Q = NAND(Sbar, Qbar) and Qbar = NAND(Rbar, Q). The inputs are active low, so a 0 on Sbar sets Q and a 0 on Rbar resets it.

Why are the inputs of a NAND SR latch active low?

A NAND output is forced to 1 whenever any input is 0, so a 0 is the value that takes control of the gate. A 1 on an input leaves the gate acting as an inverter of the other input, which is the hold condition.

What is the invalid state of a NAND SR latch?

Sbar = Rbar = 0. Both NAND outputs are forced to 1, so Q and Qbar are both 1, and if both inputs return to 1 at the same time the latch may settle either way.

What is the difference between a NAND latch and a NOR latch?

A NOR latch has active-high inputs (S = 1 sets, both 0 holds, both 1 invalid); a NAND latch has active-low inputs (Sbar = 0 sets, both 1 holds, both 0 invalid). They store a bit the same way, through cross-coupled feedback.