How to build a 8-to-1 multiplexer from logic gates

An 8-to-1 multiplexer passes one of eight data inputs D0 to D7 to a single output Y, chosen by a 3-bit select S2 S1 S0: Y = D_k where k is the select value. It is a 3-to-8 decoder whose lines each gate one data input, followed by an OR of the eight results.

Where a 4-to-1 mux uses two select lines, eight inputs need three. The structure is the same at any size: decode the select so exactly one line is 1, AND each line with its data input, and OR everything together. Only the selected data input can get through. Every one of the 2,048 input combinations (8 data bits times 8 selects) is checked before the page is built.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

3× NOT: the complements of S2, S1 and S0
12× AND: the 3-to-8 decode of the select (4 pair ANDs plus 8 line ANDs)
8× AND: gating each data input D_k with its decoded line
7× OR: a tree that merges the eight gated terms into Y

Step by step

Place the data inputs D0 to D7 and the select inputs S2, S1, S0.
Decode the select into eight one-hot lines, exactly as in the 3-to-8 decoder: line k is 1 only when S2 S1 S0 equals k.
AND each line with its data input: line 0 with D0, line 1 with D1, and so on. Seven of these ANDs output 0 no matter what; the selected one outputs its D.
Merge the eight ANDs with an OR tree: four ORs, then two, then one. Its output is Y.
Probe Y. Set a select value, then toggle the data inputs: only the selected one moves Y.

8-to-1 multiplexer truth table

S2	S1	S0	Y
0	0	0	D0
0	0	1	D1
0	1	0	D2
0	1	1	D3
1	0	0	D4
1	0	1	D5
1	1	0	D6
1	1	1	D7

As a sum of products: Y = S2'S1'S0' D0 + S2'S1'S0 D1 + ... + S2 S1 S0 D7, one term per data input. Wire the data inputs to constants and an 8-to-1 mux becomes a lookup table for any 3-input function, which is exactly how FPGA logic cells work. The 74HC151 is the classic 8-input multiplexer chip.

You can also read the full theory in the lesson on the multiplexer. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 8-to-1 multiplexer in the lab →

Frequently asked

How many select lines does an 8-to-1 multiplexer have?

Three, because 2^3 = 8. In general a 2^n-to-1 multiplexer needs n select lines.

What is the Boolean expression of an 8-to-1 multiplexer?

Y is the OR of eight terms, each a data input ANDed with one select combination: Y = S2'S1'S0'D0 + S2'S1'S0D1 + S2'S1S0'D2 + S2'S1S0D3 + S2S1'S0'D4 + S2S1'S0D5 + S2S1S0'D6 + S2S1S0D7.

How do you build an 8-to-1 mux from 4-to-1 muxes?

Use two 4-to-1 muxes on S1 S0, one for D0 to D3 and one for D4 to D7, then a 2-to-1 mux controlled by S2 to pick between their outputs.

How can a multiplexer implement any Boolean function?

Connect the function's variables to the select lines and tie each data input to the function's value (0 or 1) for that row of the truth table. The mux then outputs the function. An 8-to-1 mux implements any 3-variable function this way.