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How to build a D latch from logic gates

A gated D latch stores one bit: while the enable input EN is 1 the output Q follows the data input D, and when EN drops to 0, Q holds the last value. It is an SR latch with two AND gates and a NOT in front.

The plain SR latch remembers a bit but has a forbidden input (S and R both 1) and two separate control lines. The D latch fixes both: one data line D decides what to store, and one enable line EN decides when. The AND gates make sure S and R can never both be 1, so the forbidden case simply cannot happen. The live circuit starts transparent (EN = 1), so Q follows D straight away; turn EN off and Q freezes.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

Step by step

  1. Build an SR latch from two cross-coupled NOR gates. The NOR fed by R gives Q; the NOR fed by S gives Q̄ (Q-bar).
  2. Place a data input D and an enable input EN.
  3. Make the set signal: AND D with EN and wire it to the latch's S input.
  4. Make the reset signal: invert D with a NOT gate, AND it with EN, and wire it to the latch's R input. Now S and R are never 1 together.
  5. Probe Q and Q̄. With EN = 1, toggle D and Q follows. Set EN = 0 and toggle D again: Q stays put. That is the stored bit.

D latch truth table

ENDQ (next)
0xhold
100
111

While enabled the latch is transparent: Q is a copy of D, and any change on D passes straight through. While disabled it is opaque and holds. That level-sensitive behaviour is the difference from a D flip-flop, which samples D only at a clock edge; a flip-flop is two of these latches back to back.

You can also read the full theory in the lesson on the gated D latch. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the D latch in the lab →

Frequently asked

How does a gated D latch work?

Two AND gates turn D and EN into the set and reset inputs of an SR latch. While EN is 1, D = 1 sets the latch and D = 0 resets it, so Q follows D. While EN is 0, both AND outputs are 0, which is the SR latch's hold state, so Q keeps its value.

What is the difference between a D latch and a D flip-flop?

A D latch is level-triggered: Q follows D for the whole time EN is high. A D flip-flop is edge-triggered: it captures D only at the clock's rising (or falling) edge and ignores D the rest of the time. A D flip-flop is built from two D latches enabled on opposite clock levels.

Why does the D latch not have a forbidden state?

Its S input is D AND EN and its R input is NOT D AND EN. D and NOT D can never both be 1, so S and R can never both be 1, which is the SR latch's forbidden combination.

How many gates does a D latch need?

This one uses five: two NOR gates for the SR latch, two AND gates and one NOT. A version with four NAND gates plus an inverter (or four NANDs with D and NOT D) is also common, since an SR latch can be built from cross-coupled NANDs.