How to build a JK flip-flop from logic gates

A JK flip-flop is the most versatile flip-flop: on each clock edge it can hold, set, reset, or toggle. This one is built from a D flip-flop driven by the JK logic D = J AND NOT Q, OR NOT K AND Q, plus a clear input to start it from a known state.

The JK flip-flop removes the SR flip-flop's one forbidden input combination and puts it to work: where SR with both inputs high is illegal, JK with both inputs high toggles. The trick is to feed a plain edge-triggered D flip-flop the value D = J AND NOT Q, OR NOT K AND Q, so the current output Q loops back into the next-state logic. Because that feedback leaves Q undefined at power-on, the circuit also has an active-high clear (CLR) that forces Q to 0 to get it started.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

1× D flip-flop — the edge-triggered storage (master and slave latches plus a clock inverter, each latch built from gates)
2× AND — the two next-state terms, J AND NOT Q and NOT K AND Q
1× OR — combining them into D = J AND NOT Q, OR NOT K AND Q
3× NOT — NOT K, NOT Q for the feedback, and the CLR mask that forces Q to 0

Step by step

Start from an edge-triggered D flip-flop: it captures whatever is on its D input at each rising clock edge and holds it. That is the storage element.
Feed the output Q back into the next-state logic. Compute NOT Q and NOT K with two NOT gates.
Form the two next-state terms: AND gives J AND NOT Q (this sets Q when J is 1) and NOT K AND Q (this keeps Q when K is 0). OR them together to make D = J AND NOT Q, OR NOT K AND Q, and wire that into the D flip-flop's input.
Add the clear: a CLR input through a NOT gate masks the output so Q is forced to 0 while CLR is high. Pulse CLR high once on power-up so Q starts defined (the feedback cannot start itself from a floating output).
Probe Q. With CLR low, step the clock and watch the four modes: J=K=0 holds, J=1 K=0 sets, J=0 K=1 resets, and J=K=1 toggles Q on every edge.

JK flip-flop truth table

J	K	Q (next)
0	0	hold
0	1	0
1	0	1
1	1	toggle

The last row is what makes the JK special: with both inputs high it toggles, flipping Q on every clock edge. That is exactly the behaviour a counter needs, so a chain of toggling JK flip-flops is the simplest binary counter. The values here are the next state Q takes on the clock edge, not the instant output.

You can also read the full theory in the lesson on the JK flip-flop. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

half adder full adder half subtractor full subtractor 2:1 multiplexer 4:1 multiplexer XOR gate from NAND gates 2-to-4 decoder SR latch D flip-flop

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab and course.

Open the JK flip-flop in the lab →

Frequently asked

What is the truth table of a JK flip-flop?

By J and K at the clock edge: 0,0 holds Q, 0,1 resets Q to 0, 1,0 sets Q to 1, and 1,1 toggles Q (flips it). In one line, Q(next) = J AND NOT Q, OR NOT K AND Q.

How do you build a JK flip-flop using NAND gates?

A JK flip-flop is a clocked (usually master-slave) flip-flop with its J and K inputs gated by the fed-back outputs Q and NOT Q. Because NAND is universal, every gate here (the AND, OR and NOT of the next-state logic and the latches inside the D flip-flop) can be built from NAND gates alone, which is how the classic 7476-style JK is drawn entirely in NANDs. This build shows the same logic with named gates so each role is clear.

What is the difference between a JK and an SR flip-flop?

An SR flip-flop has a forbidden input (S=R=1 drives both outputs the same and leaves the next state undefined). A JK flip-flop defines that case as toggle: J=K=1 flips the output on each clock edge. Otherwise J behaves like S (set) and K like R (reset).

Why does this JK flip-flop have a clear input?

Its output feeds back into its own next-state logic, so at power-on there is no defined Q to compute the next state from and the flip-flop would float. Pulsing the active-high CLR forces Q to 0, giving the feedback a known starting point. Real JK flip-flops such as the 7476 include a preset and clear for the same reason.