How to build a T flip-flop from logic gates

A T flip-flop is a D flip-flop whose input is D = T XOR Q: with T = 0 it holds its bit, and with T = 1 it toggles on every rising clock edge, so its characteristic equation is Q+ = T XOR Q.

The T (toggle) flip-flop is the JK flip-flop with J and K tied together: one input that either keeps the bit or flips it. You do not need a special cell to get one. Feed an ordinary edge-triggered D flip-flop the XOR of T and its own output, and the XOR does the deciding: XOR with 0 passes Q through unchanged, XOR with 1 inverts it. This build adds a synchronous RESET so the feedback loop starts from a known 0.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

1× D flip-flop: the edge-triggered storage (master and slave D latches plus a clock inverter, each latch built from gates)
1× XOR: the next-state logic T XOR Q
1× AND: masking the next state to 0 while RESET is high
1× NOT: inverting RESET for that mask

Step by step

Place a clock CLK, a toggle input T, a RESET input, and one edge-triggered D flip-flop. Wire CLK to the flip-flop's clock.
Feed the flip-flop's output Q back into an XOR gate together with T. Its output, T XOR Q, is the next state: equal to Q when T is 0, the opposite of Q when T is 1.
Add the reset: invert RESET with a NOT gate and AND it with the XOR output. Wire that AND output into the flip-flop's D, so D is forced to 0 while RESET is high.
Probe Q. Hold RESET high for one clock edge so Q starts at 0 (the feedback cannot define itself from a floating output), then release it.
Now set T = 1 and watch Q flip on every rising edge, a square wave at half the clock frequency. Set T = 0 and Q freezes at whatever it last held.

T flip-flop truth table

T	Q	Q+ (next)
0	0	0
0	1	1
1	0	1
1	1	0

Read it as two modes: the T = 0 rows hold (Q+ equals Q) and the T = 1 rows toggle (Q+ is the opposite of Q). That is exactly the XOR truth table, which is why the characteristic equation is Q+ = T XOR Q. Run it backwards and you get the excitation equation used to design counters: to move from Q to a wanted Q+, set T = Q XOR Q+.

You can also read the full theory in the lesson on the T flip-flop. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the T flip-flop in the lab →

Frequently asked

How do you make a T flip-flop from a D flip-flop?

Connect an XOR gate in front of the D input: one XOR input is T, the other is the flip-flop's own output Q, and the XOR output drives D. Then D = T XOR Q, so the flip-flop holds when T is 0 and toggles when T is 1.

What is the characteristic equation of a T flip-flop?

Q+ = T XOR Q (also written Q+ = TQ' + T'Q). Since XOR is symmetric, Q+ = Q XOR T is the same equation. The excitation equation, which gives the T needed for a wanted transition, is T = Q XOR Q+.

Why does a T flip-flop divide the clock frequency by 2?

With T held at 1, Q flips once per rising clock edge, so it takes two clock cycles for Q to go high and back low. Q is a square wave at exactly half the clock frequency, which is why a chain of T flip-flops counts in binary.

What is the difference between a T flip-flop and a JK flip-flop?

A T flip-flop is a JK flip-flop with J and K tied together into one input T. It keeps only the hold (T = 0) and toggle (T = 1) modes and gives up the separate set and reset, which is all a counter needs.