How to build a 4-bit shift register from logic gates

A 4-bit shift register is four D flip-flops in a chain sharing one clock, each output Q wired to the next flip-flop's D input, so on every rising clock edge each stored bit moves one place along.

This one is serial-in, parallel-out (SIPO): bits enter one at a time on a single input IN and can be read four at a time on Q0 to Q3. That conversion from a serial stream to a parallel word is how a UART or SPI receiver assembles a byte, and the same chain with its last output fed back to the front becomes a ring or Johnson counter.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

4× D flip-flop: one storage stage per bit (each is two gated D latches plus a clock inverter, built from gates)
1× clock: shared by every stage so all four shift at the same instant

Step by step

Place a clock CLK, a serial input IN, and four edge-triggered D flip-flops in a row. Wire CLK to the clock input of every flip-flop.
Wire IN to the first flip-flop's D.
Chain the stages: the first flip-flop's Q drives the second's D, the second's Q drives the third's D, and the third's Q drives the fourth's D.
Probe each output as Q0 to Q3. Before any bit has reached a stage its output is still floating (Z), so let the clock run with IN = 0 for four edges to clear the register.
Now set IN high for one clock and back low, and watch that single 1 step from Q0 to Q1 to Q2 to Q3, one stage per rising edge, then fall off the end.

Shifting in the pattern 1, 0, 1, 1

Clock edge	IN	Q0	Q1	Q2	Q3
start	x	0	0	0	0
1	1	1	0	0	0
2	0	0	1	0	0
3	1	1	0	1	0
4	1	1	1	0	1

On every edge all four stages update at once: Q0 takes IN, Q1 takes the old Q0, and so on. After four edges the serial bits 1, 0, 1, 1 sit side by side in parallel, with the first bit in Q3. It works because a flip-flop samples only at the edge: each stage captures its neighbour's value from just before the edge, so a bit moves exactly one place per clock instead of racing down the whole chain.

You can also read the full theory in the lesson on shift registers. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 4-bit shift register in the lab →

Frequently asked

How does a shift register work?

It is a chain of flip-flops on one shared clock, each output feeding the next input. On each rising clock edge every flip-flop captures the value its neighbour held just before the edge, so the whole pattern moves one position per clock.

What are SISO, SIPO, PISO and PIPO shift registers?

The letters say how data gets in and out: serial or parallel. SIPO (this circuit) takes bits in one at a time and presents them all at once; PISO loads a word in parallel and sends it out one bit at a time; SISO is a pure delay line; PIPO loads and reads a whole word in parallel.

How many flip-flops does a 4-bit shift register need?

Four, one per bit. An n-bit shift register needs n flip-flops, all clocked together. Parallel load, shift direction control or a clear input add multiplexers or gates in front of each D input, but the storage is still one flip-flop per bit.

What is a shift register used for?

Converting between serial and parallel data (serial links such as UART and SPI), delaying a bit stream by a fixed number of clocks, multiplying or dividing by 2 with a shift, and, with the output fed back to the input, building ring and Johnson counters.