How to build a 4-bit synchronous counter from logic gates

A 4-bit synchronous binary counter counts 0 to 15 and wraps, with all four flip-flops on one shared clock: bit k flips on a clock edge exactly when every lower bit is 1, so its next value is Q_k XOR (Q_k-1 AND ... AND Q₀).

That rule is binary counting itself: adding 1 flips the lowest bit, and the carry keeps flipping bits upward for as long as it meets 1s. Because every flip-flop is clocked at the same instant, all the bits change together, unlike a ripple counter where each stage clocks the next and the bits settle one after another. This build has a synchronous CLR; in the live circuit the clock is already running, so turn CLR on for one tick and off again, then watch it count.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

4× D flip-flop: one per bit, all on the same clock (each is two gated D latches plus a clock inverter)
3× XOR: next state of bits 1 to 3: Q_k XOR (all lower bits are 1)
2× AND: the toggle chain Q1 Q0 and Q2 Q1 Q0
4× AND: masking each D input with NOT CLR for the synchronous clear
2× NOT: NOT Q0 (bit 0 toggles every clock) and NOT CLR

Step by step

Place a clock CLK, a CLR input and four D flip-flops for Q0 to Q3, all clocked by CLK.
Bit 0 toggles on every edge: feed NOT Q0 to its D input.
Bit 1 toggles when Q0 is 1: its next state is Q1 XOR Q0. Bit 2 toggles when Q1 and Q0 are both 1: build Q1 AND Q0 and use Q2 XOR (Q1 AND Q0). Bit 3 uses Q3 XOR (Q2 AND Q1 AND Q0), extending the AND chain.
Add the clear: AND each next-state signal with NOT CLR before it reaches D, so a clock edge with CLR high loads 0000. It also gives the feedback loop a defined starting value.
Probe Q0 to Q3. Pulse CLR for one clock, release it, and read Q3 Q2 Q1 Q0 as a binary number: 0001, 0010, 0011, and on up to 1111, then 0000.

Counting sequence

Clock edge	Q3	Q2	Q1	Q0	Count
CLR	0	0	0	0	0
1	0	0	0	1	1
2	0	0	1	0	2
3	0	0	1	1	3
4	0	1	0	0	4
7	0	1	1	1	7
8	1	0	0	0	8
15	1	1	1	1	15
16	0	0	0	0	0

Watch edges 7 to 8: Q0, Q1 and Q2 are all 1, so all four bits toggle on the same edge, 0111 to 1000, with no in-between values. Each output is also a frequency divider: Q0 runs at half the clock frequency, Q1 at a quarter, Q2 at an eighth and Q3 at a sixteenth. The full 0 to 15 sequence and the wrap back to 0 are checked over 19 clock cycles before the page is built.

You can also read the full theory in the lesson on synchronous counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 4-bit synchronous counter in the lab →

Frequently asked

What is a synchronous counter?

A counter whose flip-flops all share one clock, so every bit that changes does so on the same edge. Next-state logic (here an AND chain and XORs) decides which bits toggle, instead of each flip-flop being clocked by the previous one.

What is the difference between a synchronous and an asynchronous (ripple) counter?

In a ripple counter each flip-flop is clocked by the output of the one before it, so a change ripples through the stages and the outputs briefly show wrong values. In a synchronous counter every flip-flop is clocked together and all bits change at once, which is faster and glitch-free at the cost of some gates.

How many flip-flops does a 4-bit counter need?

Four. An n-bit binary counter has n flip-flops and counts 2^n states, so four flip-flops count 0 to 15.

How do you make a synchronous counter from T flip-flops?

Connect T0 = 1, T1 = Q0, T2 = Q1 Q0, T3 = Q2 Q1 Q0. A T flip-flop toggles when T = 1, which is exactly the rule here. This page builds the same thing from D flip-flops, using D = Q XOR T, which is what a T flip-flop is inside.