How to build a 4-bit up/down counter from logic gates

A 4-bit synchronous up/down counter counts up (0, 1, 2, ...) when its UP input is 1 and down (..., 2, 1, 0) when UP is 0, wrapping between 15 and 0. Bit k toggles on a clock edge when every lower bit is 1 counting up, or every lower bit is 0 counting down.

Counting down is counting up with the bits read inverted, so the direction control is one XNOR per bit: t_i = Q_i XNOR UP passes Q_i through when UP = 1 and inverts it when UP = 0. The rest is the synchronous up counter: an AND chain over those t signals decides which bits toggle. In the live circuit the clock is already running and UP starts at 1: turn CLR on for one tick and off, watch it count up, then switch UP off and watch it count back down through 0 to 15.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

4× D flip-flop: one per bit, all on the same clock
3× XNOR: direction: t_i = Q_i XNOR UP for bits 0 to 2
2× AND: the toggle chain t0 t1 and t0 t1 t2
3× XOR: next state of bits 1 to 3: Q_k XOR (toggle condition)
4× AND: masking each D input with NOT CLR (synchronous clear)
2× NOT: NOT Q0 (bit 0 always toggles) and NOT CLR

Step by step

Place a clock CLK, a direction input UP, a CLR input and four D flip-flops for Q0 to Q3.
Bit 0 toggles on every edge in both directions: feed NOT Q0 to its D.
For bits 0 to 2 build t_i = Q_i XNOR UP: it is Q_i when counting up and NOT Q_i when counting down.
Chain them: bit 1 toggles when t0 = 1, bit 2 when t0 AND t1, bit 3 when t0 AND t1 AND t2. Each next state is Q_k XOR its toggle condition.
AND every next-state signal with NOT CLR before its D input, then probe Q0 to Q3. Pulse CLR, count up a few steps, set UP = 0 and count down past zero.

Counting up, then down

Clock edge	UP	Q3 Q2 Q1 Q0	Count
CLR	x	0000	0
1	1	0001	1
2	1	0010	2
3	1	0011	3
4	0	0010	2
5	0	0001	1
6	0	0000	0
7	0	1111	15
8	0	1110	14

Edge 7 is the down-count wrap: at 0000 every t_i is 1 (all bits are 0 while counting down), so all four bits toggle together into 1111. The verification run counts up from 0 to 5 and back down through 0 to 14, checking all four bits at every clock.

You can also read the full theory in the lesson on synchronous counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 4-bit up/down counter in the lab →

Frequently asked

How does an up/down counter work?

Counting up, a bit toggles when all lower bits are 1. Counting down, a bit toggles when all lower bits are 0. A direction input selects which condition is used, usually by passing each Q or NOT Q into the toggle logic with an XNOR or a 2-to-1 multiplexer.

How do you design a synchronous up/down counter with T flip-flops?

Use T0 = 1 and, for higher bits, T_k = UP(Q_{k-1}...Q_0) + UP'(Q'_{k-1}...Q'_0). This page uses the equivalent form t_i = Q_i XNOR UP with an AND chain, and builds each T flip-flop as a D flip-flop with D = Q XOR T.

What happens when an up/down counter counts below zero?

It wraps around. A 4-bit counter going down from 0000 toggles every bit and lands on 1111 (15), just as counting up from 15 wraps to 0.

What is the 74HC191?

A common 4-bit synchronous up/down binary counter chip, with a single direction input and parallel load. The 74HC193 is a similar counter with separate up and down clock inputs.