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How to build a full adder using only NAND gates

A full adder can be built from nine NAND gates: two 4-NAND XORs make the sum S = A XOR B XOR Cin, and one more NAND combines two signals those XORs already produce into the carry Cout = (A AND B) OR (Cin AND (A XOR B)).

It is two NAND half adders with the carry logic folded in. The first NAND of each XOR stage, NAND(A, B) and NAND(A XOR B, Cin), is exactly an inverted carry term, and NANDing two inverted terms is an OR (De Morgan again), so the final carry costs a single gate. Compare it with the full adder from XOR, AND and OR: same truth table, nine gates of one kind instead of five of three kinds.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

Step by step

  1. Place inputs A, B and Cin.
  2. Build A XOR B from four NANDs: N1 = NAND(A, B), then NAND(A, N1) and NAND(B, N1), then NAND those two.
  3. Build the sum the same way from (A XOR B) and Cin: N4 = NAND(A XOR B, Cin), then NAND(A XOR B, N4) and NAND(Cin, N4), then NAND those two. That output is S.
  4. The carry: Cout = NAND(N1, N4). N1 is NOT(A AND B) and N4 is NOT(Cin AND (A XOR B)), so NANDing them ORs the two carry terms.
  5. Probe S and Cout and check all eight rows against the table below.

Full adder truth table

ABCinSCout
00000
00110
01010
01101
10010
10101
11001
11111

Nine NANDs is the usual minimum for a full adder from 2-input NAND gates. Each NAND is four CMOS transistors, so this is a 36-transistor adder; a ripple-carry adder for 8-bit numbers chains eight of them.

You can also read the full theory in the lesson on the full adder. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

half adderfull adderhalf subtractorfull subtractor2:1 multiplexer4:1 multiplexerXOR gate from NAND gates2-to-4 decoderSR latchD flip-flopJK flip-flopT flip-flop4-bit shift register4-bit ripple carry adderD latch1-to-4 demultiplexer4-bit magnitude comparator4-bit ring counter4-bit Johnson counter4-to-2 priority encoder4-bit synchronous counter3-to-8 decoder8-to-1 multiplexer4-bit carry lookahead adderhalf adder from NAND gates2-bit comparatorBCD to 7-segment decoder4-bit up/down counterdecade counter2-bit multiplier4-bit ALU4-bit array multiplierNOT, AND, OR and NOR from NANDNOT, OR, AND and XOR from NORSR latch from NAND gatesparity generator and checker4-bit adder/subtractorBCD adder4-bit universal shift register

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the full adder from NAND gates in the lab →

Frequently asked

How many NAND gates are needed for a full adder?

Nine. Two 4-NAND XOR stages produce the sum, and a ninth NAND combines the first gate of each XOR stage into the carry-out.

How does the carry work in a NAND full adder?

The first gate of each XOR stage outputs an inverted carry term: NAND(A, B) = NOT(AB) and NAND(A XOR B, Cin) = NOT(Cin(A XOR B)). NANDing two inverted terms gives their OR, which is exactly Cout = AB + Cin(A XOR B).

Can a full adder be built from NOR gates only?

Yes. NOR is universal too, so any circuit can be built from it; see how NOT, OR, AND and XOR are made from NOR gates. The NAND version is the more common textbook exercise because its carry falls out of the XOR stages so neatly.

Is a NAND-only full adder slower?

The sum passes through up to six NAND levels, more than the XOR/AND/OR version's gate levels, but each NAND is a fast, small CMOS gate. When adders are chained, what matters most is the carry-in to carry-out path, and here that is only two NAND levels.