How to build a 4-bit array multiplier from logic gates

A 4-bit array multiplier multiplies two 4-bit numbers A and B into an 8-bit product P7..P0: sixteen AND gates form every partial product A_j B_i, and three rows of adders add the shifted rows together, exactly like long multiplication on paper.

It is the 2-bit multiplier grown to four bits. Multiplying by one bit of B is just ANDing it with every bit of A, so each row of partial products costs four AND gates. Row by row, an adder adds the next row, shifted one place left, to the running total; the lowest bit of each sum drops out as a finished product bit. With the gates here (half adders where a column has only two inputs, full adders elsewhere) that is 64 gates, and all 256 input pairs are checked against real multiplication before the page is built.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

16× AND: the partial products A_j AND B_i
8× full adder: inside the three adder rows (each 2 XOR, 2 AND, 1 OR)
4× half adder: where a column has only two bits to add (each 1 XOR, 1 AND)

Step by step

Place inputs A3 to A0 and B3 to B0, and build all sixteen partial products A_j AND B_i.
Row 0 is A times B0. Its lowest bit, A0 B0, is already the finished P0.
Add row 1 (A times B1, shifted one place left) to the remaining bits of row 0 with a 4-bit adder. Its lowest sum bit is P1; keep the other bits and the carry.
Repeat for row 2 (giving P2) and row 3 (giving P3). The last adder's remaining sum bits and carry are P4 to P7.
Probe P7 to P0 and try 1111 x 1111: the product is 11100001, which is 15 x 15 = 225.

Example products

A	B	A x B	P7..P0
0011	0101	3 x 5 = 15	00001111
0110	0111	6 x 7 = 42	00101010
1010	1010	10 x 10 = 100	01100100
1111	1111	15 x 15 = 225	11100001

An n-bit by n-bit multiplier needs 2n product bits, here 8, because 15 x 15 = 225 needs eight bits. The cost grows with n squared (n² AND gates and about n² adders), which is why some small processors skip a hardware multiplier and multiply in software with shift-and-add, the same algorithm this array lays out in space.

You can also read the full theory in the lesson on binary multiplication. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 4-bit array multiplier in the lab →

Frequently asked

How does a 4-bit array multiplier work?

Sixteen AND gates make the partial products A_j AND B_i. Each row of four partial products is shifted one place left of the previous row, and rows of adders sum them, so the product bits come out one per row at the low end and the final adder supplies the top bits.

How many AND gates and adders does a 4-bit multiplier need?

Sixteen AND gates, one per pair of bits. The adder array needs three rows; with half adders where a column has only two inputs, this design uses eight full adders and four half adders.

Why is the product of two 4-bit numbers 8 bits?

The largest product is 15 x 15 = 225, which needs eight bits. In general an n-bit times n-bit product needs up to 2n bits.

What is the difference between an array multiplier and shift-and-add?

They do the same arithmetic. Shift-and-add reuses one adder over several clock cycles, adding one partial product per cycle. An array multiplier lays out an adder for every row so the whole product is computed at once, faster but with far more gates.