Edge detector circuit: rising and falling edges, live

An edge detector turns a change in a signal into a pulse one clock long. This synchronous one samples IN with two D flip-flops, so Q1 holds IN now and Q2 holds IN one clock earlier: RISE = Q1 AND NOT Q2 marks a 0-to-1 change and FALL = Q2 AND NOT Q1 marks a 1-to-0 change.

A button or a slow sensor stays at 1 for many clocks, but a counter or a state machine usually needs to react once per press. Comparing a signal with its own value one clock earlier solves that: the two differ for exactly one clock after each change. The first flip-flop also synchronizes IN to the clock, so RISE and FALL change only on clock edges. When IN comes from outside the clock domain, real designs put one more flip-flop in front to guard against metastability, and a mechanical button also needs debouncing first. RISE and FALL are checked at every one of 10 clocks before the page is built. In the live circuit the clock is already running: flip IN and watch RISE or FALL light for one clock.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× D flip-flop: Q1 = IN sampled on each clock, Q2 = Q1 one clock later
2× NOT: NOT Q1 and NOT Q2
2× AND: RISE = Q1 AND NOT Q2, FALL = Q2 AND NOT Q1

Step by step

Place a clock CLK, an input IN, and probes RISE and FALL.
Chain two D flip-flops on the same clock: IN into the first, its Q into the second.
RISE: AND the first flip-flop's Q with the inverted Q of the second.
FALL: AND the second flip-flop's Q with the inverted Q of the first.
Turn IN on: RISE is 1 for one clock. Turn it off: FALL is 1 for one clock.

Edge detector timing

Clock	IN	Q1 (now)	Q2 (before)	RISE	FALL
1	1	1	0	1	0
2	1	1	1	0	0
3	1	1	1	0	0
4	0	0	1	0	1
5	0	0	0	0	0
6	1	1	0	1	0
7	0	0	1	0	1
8	1	1	0	1	0
9	1	1	1	0	0

Each row is the state just after a rising clock edge, with IN as it was sampled on that edge. This is the sequence checked before the page is built; its first clock, before Q2 has a value, is not shown.

You can also read the full theory in the lesson on the D flip-flop. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the edge detector in the lab →

Frequently asked

What is an edge detector circuit?

A circuit that outputs a short pulse when its input changes: a rising edge detector pulses when the input goes from 0 to 1, and a falling edge detector when it goes from 1 to 0.

How do you detect a rising edge with a flip-flop?

Store the input in a D flip-flop on every clock and AND the current sample with the inverted stored one. The result is 1 only during the clock after the input rose. Sampling the input into a first flip-flop as well, as here, keeps the pulse aligned to the clock.

Why not detect edges with a gate and a delay?

A gate fed with a signal and a delayed, inverted copy of it does give a short pulse, but its width depends on gate delays that change with temperature and voltage. A clocked detector gives a pulse exactly one clock long.

What is the difference between an edge detector and a debouncer?

A debouncer cleans up a noisy mechanical switch so that one press gives one clean transition; an edge detector then turns that transition into a single one-clock pulse. Button inputs usually need both.