CMOS NAND gate: four transistors, live

A CMOS NAND gate uses four transistors: two PMOS in parallel from the supply to the output, and two NMOS in series from the output to ground. The output is 0 only when both inputs are 1, because only then do both series NMOS conduct while both PMOS are off.

The pull-down network (the NMOS) and the pull-up network (the PMOS) are duals of each other. NMOS in series form an AND condition, so the output is pulled to 0 only when A AND B are both 1; PMOS in parallel form an OR of the inverted inputs, so the output is pulled to 1 whenever A or B is 0. For every input exactly one network conducts. NAND is the cheapest useful gate in CMOS, and because it is universal, every other gate can be built from it. Read more about pull-down and pull-up networks, or compare the CMOS NOR gate, which swaps series and parallel.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× PMOS transistor: in parallel between VDD and the output, one gated by A and one by B
2× NMOS transistor: in series between the output and GND, one gated by A and one by B

Step by step

Place VDD, GND, inputs A and B, and a probe Y on the output node.
Pull-up: put two PMOS side by side, each from VDD to the output, one with its gate on A and one on B.
Pull-down: put two NMOS in a stack from the output to GND, one gated by A and one by B.
Try all four input pairs: only A = B = 1 turns both NMOS on (and both PMOS off), giving Y = 0.

CMOS NAND truth table, transistor by transistor

A	B	PMOS A	PMOS B	NMOS A	NMOS B	Y
0	0	on	on	off	off	1
0	1	on	off	off	on	1
1	0	off	on	on	off	1
1	1	off	off	on	on	0

In the first three rows at least one PMOS is on and the NMOS stack is broken, so Y is pulled to 1. Only the last row closes the whole stack. All four rows are checked on the live circuit before the page is built.

You can also read the full theory in the lesson on the NAND gate. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

half adder full adder half subtractor full subtractor 2:1 multiplexer 4:1 multiplexer XOR gate from NAND gates 2-to-4 decoder SR latch D flip-flop JK flip-flop T flip-flop 4-bit shift register 4-bit ripple carry adder D latch 1-to-4 demultiplexer 4-bit magnitude comparator 4-bit ring counter 4-bit Johnson counter 4-to-2 priority encoder 4-bit synchronous counter 3-to-8 decoder 8-to-1 multiplexer 4-bit carry lookahead adder half adder from NAND gates 2-bit comparator BCD to 7-segment decoder 4-bit up/down counter decade counter 2-bit multiplier 4-bit ALU 4-bit array multiplier NOT, AND, OR and NOR from NAND NOT, OR, AND and XOR from NOR full adder from NAND gates SR latch from NAND gates parity generator and checker 4-bit adder/subtractor BCD adder 4-bit universal shift register mod-6 counter 4-bit ripple counter binary to Gray code converter half adder from NOR gates full adder from NOR gates 4-bit register with parallel load 1011 sequence detector binary to BCD converter D flip-flop from NAND gates 1-bit ALU CMOS inverter CMOS NOR gate PISO shift register SR flip-flop from NAND gates BCD to excess-3 code converter

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the CMOS NAND gate in the lab →

Frequently asked

How many transistors are in a CMOS NAND gate?

Four for a 2-input NAND: two PMOS in parallel and two NMOS in series. An n-input NAND uses n of each.

Why are the NMOS in series in a NAND gate?

Because the output must be pulled to 0 only when every input is 1. Series switches conduct only when all of them are on, which is exactly that AND condition.

Why is NAND preferred over NOR in CMOS?

A NAND puts its NMOS in series and its PMOS in parallel. PMOS transistors conduct more weakly than NMOS, so stacking the stronger NMOS costs less than stacking PMOS, as a NOR gate must. NAND gates are usually smaller or faster for the same drive.

How do you make an AND gate from transistors?

Add a CMOS inverter after the NAND: six transistors in total. CMOS gates naturally invert, so AND and OR are built as NAND and NOR followed by a NOT.