How to build a 4-bit register with parallel load

A 4-bit register with parallel load is four D flip-flops on one clock, each fed by a 2-to-1 multiplexer: when LD is 1 the next clock edge copies the inputs I3 to I0 into Q3 to Q0 all at once, and when LD is 0 each flip-flop gets its own output back and holds its bit.

A bare D flip-flop loads on every clock edge, so to make it hold you give it back its own value. The multiplexer in front of each D picks the new input when LD is 1 and the flip-flop's own Q when LD is 0. The clock itself is never switched off, which keeps every flip-flop on one clean, shared clock (gating the clock with LD would add delay and can create false edges). This is the same register a CPU uses for its accumulator and instruction register, just four bits wide; the 8-bit register lesson builds the byte version. In the live circuit the clock is already running and LD starts at 1 with every input at 0, so the register shows 0000: set some inputs and Q copies them on the next tick, then turn LD off and change the inputs again, and Q keeps the old value.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

4× D flip-flop: one per bit, all on the same clock
4× AND: load path: I AND LD
4× AND: hold path: Q AND NOT LD
4× OR: join the two paths into each D input (with the ANDs, a 2-to-1 mux per bit)
1× NOT: NOT LD, shared by all four bits

Step by step

Place a clock CLK, a load input LD, data inputs I3 to I0 and four D flip-flops, all clocked by CLK.
For each bit, AND the data input with LD: that is the value to load.
AND the flip-flop's own Q with NOT LD: that is the value to keep.
OR the two into the flip-flop's D input. Exactly one of the ANDs can be 1 at a time, so D = I when LD = 1 and D = Q when LD = 0.
Probe Q3 to Q0. With LD on, change the inputs and watch Q follow on the next clock; turn LD off and the register holds whatever it last loaded.

Load and hold sequence

Clock edge	LD	I3 I2 I1 I0	Q3 Q2 Q1 Q0
1	1	1010	1010
2	0	0101	1010
3	0	1111	1010
4	1	0101	0101
5	0	0000	0101
6	1	1111	1111
7	1	0011	0011
8	0	1100	0011

This is the exact run checked before the page is built: all four outputs after each of the 8 clocks. When LD is 0 the inputs can change freely (edges 2, 3, 5 and 8) without touching Q; when LD is 1 the whole word is replaced at once, which is what "parallel" load means.

You can also read the full theory in the lesson on the register bit. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 4-bit register with parallel load in the lab →

Frequently asked

What is a register with parallel load?

A group of flip-flops that share one clock and one load control, so all the bits are written at the same clock edge when load is 1 and keep their values when it is 0. Parallel means every bit is loaded at once, as opposed to a shift register, which takes one bit per clock.

How many flip-flops does a 4-bit register need?

Four, one per bit. An n-bit register uses n flip-flops plus one 2-to-1 multiplexer per bit for the load control.

Why not just turn the clock off to hold the value?

Gating the clock with an AND gate delays it and can produce a glitch, a false clock edge, when the enable changes while the clock is high. Keeping the clock running and choosing D with a multiplexer gives every flip-flop the same clean clock.

What is the difference between a register and a shift register?

A register loads all its bits in parallel from separate inputs and holds them. A shift register passes bits from one flip-flop to the next on each clock. The universal shift register combines both: it can hold, shift either way, or load in parallel.

Is a PIPO shift register the same as a register with parallel load?

Yes. PIPO (parallel-in, parallel-out) means every bit is loaded at once and every bit is visible at once, which is exactly this circuit. Unlike SISO, SIPO and PISO shift registers, it never moves bits between stages.