How to build a 4-bit ripple (asynchronous) counter

A ripple counter, or asynchronous counter, chains toggling flip-flops so that each one is clocked by the output of the one before it. Four of them count 0 to 15 in binary and wrap, and only the first flip-flop sees the real clock.

A D flip-flop with its Q' output fed back to D flips on every clock edge, which makes it a divide-by-2. Chain four of them, clocking each stage from the Q' of the stage below, and bit k flips exactly when bit k-1 falls from 1 to 0: that is binary counting, with the carry passed along as a clock edge. Because the stages have no common clock, the clear has to be asynchronous: CLR forces every flip-flop to 0 at once, whatever its clock is doing. Each flip-flop here is a master-slave pair of SR latches with that clear built in, all from basic gates, and it is checked on its own before the counter is. In the live circuit the clock is already running: turn CLR on and off once, then watch it count.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

4× D flip-flop with clear: one per bit, D tied to its own Q' so it toggles on every edge it sees
2× SR latch: inside each flip-flop: master and slave
13× gates: inside each flip-flop: 6 AND, 2 OR and 5 NOT for the clock gating, the clear and Q'

Step by step

Place a clock CLK, a CLR input and four D flip-flops with clear, one for each of Q0 to Q3.
Make every stage toggle: wire each flip-flop's Q' output back to its own D input.
Clock only bit 0 from CLK. Clock bit 1 from Q0', bit 2 from Q1' and bit 3 from Q2'. A rising edge on Q' is a falling edge on Q, so each stage flips when the one below it rolls over from 1 to 0.
Wire CLR to the clear input of all four flip-flops, so one switch resets the whole counter even though the stages are clocked at different times.
Probe Q0 to Q3, turn CLR on and off, and read Q3 Q2 Q1 Q0 as a binary number: 0001, 0010, 0011, and on up to 1111, then 0000.

Ripple counter sequence

Clock pulse	Q3	Q2	Q1	Q0	Count
CLR	0	0	0	0	0
1	0	0	0	1	1
2	0	0	1	0	2
3	0	0	1	1	3
4	0	1	0	0	4
7	0	1	1	1	7
8	1	0	0	0	8
15	1	1	1	1	15
16	0	0	0	0	0

The run checks all four bits at every one of 24 clocks: a clear from the power-on state, the count up through the 15 to 0 wrap, and a second clear in the middle of counting. Each output is also a frequency divider: Q0 runs at half the clock, Q1 at a quarter, Q2 at an eighth and Q3 at a sixteenth. On real hardware the bits do not change together: going from 7 to 8, Q0 falls first, which clocks Q1, which clocks Q2, so the outputs pass briefly through 0110, 0100 and 0000 before settling on 1000. The simulator settles each clock edge completely before showing it, so the live circuit shows only the final count. The synchronous counter avoids those in-between codes by clocking every bit at once.

You can also read the full theory in the lesson on counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 4-bit ripple counter in the lab →

Frequently asked

What is a ripple counter?

A counter made of toggle flip-flops in a chain, where only the first flip-flop gets the clock and every other one is clocked by the output of the stage before it. The change ripples from bit 0 upward, which gives it its name.

Why is a ripple counter called asynchronous?

Because its flip-flops do not share a clock. Each stage changes only after the stage below it has changed, so the bits update one after another instead of at the same instant.

What is the difference between a ripple counter and a synchronous counter?

A ripple counter needs no logic between stages but its delay grows with every bit, and its outputs pass through wrong values while a change ripples through. A synchronous counter clocks every flip-flop together and adds gates that decide which bits toggle, so all bits change at once and it can run faster.

How do you make a ripple counter count down?

With rising-edge flip-flops, clock each stage from the Q output of the stage below instead of Q'. Each bit then flips when the bit below rises from 0 to 1, which counts 15, 14, 13 and so on. Reading the Q' outputs of an up counter also gives the down count.

How many flip-flops does a ripple counter need?

One per bit. With n flip-flops it counts 2^n states, from 0 to 2^n - 1, so a 4-bit ripple counter (four flip-flops) counts 0 to 15. Chips such as the 74HC393 package two 4-bit ripple counters.