How to build a D flip-flop using only NAND gates

A positive-edge D flip-flop can be built from nine NAND gates: one NAND inverts the clock, and two 4-NAND gated D latches act as master and slave, so Q takes the value of D only at the rising edge of the clock.

Each gated D latch is four NANDs. The first, N1 = NAND(D, EN), is the inverted D while the latch is enabled, so the second, N2 = NAND(N1, EN), is D itself and no separate inverter is needed. N1 and N2 drive a cross-coupled NAND pair as active-low set and reset, and when EN is 0 both are 1, so the pair holds. The master latch is enabled by the inverted clock and the slave by the clock, so they are never open together: the master follows D while CLK is 0, and the slave copies the master's frozen value when CLK rises. The same master-slave idea built from latch blocks is on the D flip-flop page; here every gate is visible. In the live circuit the clock is already running and D starts at 0.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

1× NAND: both inputs tied to CLK: the inverted clock for the master
2× NAND: master gating: N1 = NAND(D, NOT CLK), N2 = NAND(N1, NOT CLK)
2× NAND: master SR latch (cross-coupled), set by N1 and reset by N2, both active low
2× NAND: slave gating from the master's Q, enabled by CLK
2× NAND: slave SR latch, giving Q and Qbar

Step by step

Place a clock CLK and an input D. Make NOT CLK with a NAND whose two inputs are both tied to CLK.
Build the master latch: N1 = NAND(D, NOT CLK), N2 = NAND(N1, NOT CLK), then two cross-coupled NANDs, one taking N1 and the other N2. Its output follows D while CLK is 0.
Build the slave latch the same way, but with the master's output as its data and CLK itself as the enable.
Probe the slave's two outputs as Q and Qbar.
Set D, wait for a clock tick, and Q copies it. Change D while the clock is high or low and nothing happens until the next rising edge.

D flip-flop truth table

CLK	D	Q next	Qbar next
rising edge	0	0	1
rising edge	1	1	0
no rising edge	X	Q (hold)	Qbar (hold)

Before the page is built the circuit is stepped through 12 clock and data changes with its memory carried from step to step, including D changing while the clock is high and while it is low. Q and Qbar change only on the rising edges, always to D and its complement.

You can also read the full theory in the lesson on the D flip-flop. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the D flip-flop from NAND gates in the lab →

Frequently asked

How many NAND gates are needed for a D flip-flop?

Nine in this master-slave form: four for each gated D latch and one to invert the clock. The classic edge-triggered design used in TTL chips such as the 7474 needs six NAND gates arranged as three SR latches, but its 3-input gates and racing feedback are harder to follow.

What is the difference between a D latch and a D flip-flop made of NAND gates?

The D latch is the first four NANDs alone: while its enable is 1, Q follows D continuously. The flip-flop puts two latches in series with opposite enables, so Q can change only at the rising clock edge.

Why does the master latch use the inverted clock?

So the two latches are never transparent at the same time. While CLK is 0 the master tracks D and the slave holds; when CLK rises the master freezes and the slave passes the frozen value to Q. That hand-over at the edge is what makes the flip-flop edge-triggered.

Why does a NAND D latch need only four gates?

Because the first gate, NAND(D, EN), already equals NOT D while the latch is enabled. The second gate NANDs that with EN to get D, so the set and reset signals come out complementary without a separate inverter, and S = R = 1 can never happen.