How to build a PISO shift register (parallel in, serial out)

A PISO (parallel-in, serial-out) shift register loads all its bits at once and then sends them out one bit per clock. This 4-bit one loads D3 to D0 when LD is 1, and when LD is 0 each clock shifts the word one place toward the serial output SO, most significant bit first.

Each stage is a D flip-flop with a 2-to-1 multiplexer in front of it: with LD = 1 it takes its own parallel input, with LD = 0 it takes the output of the stage before it. That one control line turns four separate inputs into a single wire, which is how a microcontroller can read many buttons through one pin with a chip such as the 74HC165, or how a serial link sends a byte. The reverse job, serial in and parallel out, is the SIPO shift register; loading and holding all four bits in parallel is the PIPO register. In the live circuit the clock is running and LD starts at 1 with all inputs 0: set a pattern on D3 to D0, then turn LD off and watch it leave through SO.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

4× D flip-flop: the four stages, all on one clock
4× AND: load path: Di AND LD
3× AND: shift path: Q of the previous stage AND NOT LD (the first stage shifts in 0)
3× OR: join load and shift paths into each D input
1× NOT: NOT LD

Step by step

Place a clock CLK, a control LD, data inputs D3 to D0 and four D flip-flops on the same clock.
In front of each flip-flop, build a 2-to-1 mux: (Di AND LD) OR (Q(i-1) AND NOT LD). The first stage has no stage before it, so it shifts in 0.
Probe the last stage as the serial output SO, and the other stages as Q2 to Q0.
With LD = 1, one clock copies D3 to D0 into the register. Set LD = 0 and every clock moves the bits one place toward SO: D3 comes out first, then D2, D1 and D0.

Load and shift sequence

Clock edge	LD	D3 D2 D1 D0	SO Q2 Q1 Q0
1	1	1011	1011
2	0	1111	0110
3	0	0000	1100
4	0	0101	1000
5	0	0000	0000
6	1	0110	0110
7	0	1001	1100
8	0	0000	1000

This is the exact run checked before the page is built, all four outputs after each of the 8 clocks. After the load on edge 1, SO reads 1, 0, 1, 1 on edges 1 to 4: the loaded word 1011, most significant bit first. While LD is 0 the parallel inputs can change freely (edges 2 to 5) without affecting the shift.

You can also read the full theory in the lesson on shift registers. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the PISO shift register in the lab →

Frequently asked

What is a PISO shift register?

A parallel-in, serial-out shift register: it loads several bits at the same clock edge and then shifts them out one bit per clock on a single output. It turns a parallel word into a serial stream.

What is the difference between SISO, SIPO, PISO and PIPO shift registers?

The letters say how data goes in and out. SISO takes one bit per clock and outputs one bit per clock (a delay line). SIPO takes serial input and shows all bits in parallel. PISO loads in parallel and outputs serially. PIPO loads and outputs all bits in parallel, which is a plain register.

Where is a PISO shift register used?

To read many inputs over few wires, for example a row of buttons into a microcontroller (the 74HC165 is a common 8-bit PISO chip), and to send a parallel word down a serial link one bit at a time.

How many clocks does a 4-bit PISO need to send a word?

One clock to load, then the most significant bit is already on the output; three more clocks bring out the other three bits. In this circuit SO shows D3 right after the load edge.