How to build a mod-6 counter from logic gates

A mod-6 counter counts 0, 1, 2, 3, 4, 5 and then returns to 0, six states per cycle, using three flip-flops. This one is a synchronous 3-bit counter whose next state is forced to 000 when the count reaches 5.

Three flip-flops can count to 7, so a mod-6 counter needs a way to cut the cycle short. Detect the last wanted state, 5 (101), and make the next clock edge load 000 instead of counting on to 6. Because the counter only passes through 0 to 5, the state 5 is the only one with both Q2 and Q0 set, so one AND gate Q2 AND Q0 is the whole detector. A mod-6 counter is half of a clock's seconds or minutes digit (0 to 5 in the tens place) and a divide-by-6 frequency divider. In the live circuit the clock is already running: pulse CLR for one tick, then watch it count.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

3× D flip-flop: the three count bits, on one clock
2× XOR: next state of bits 1 and 2 (binary counting)
1× AND: Q1 AND Q0, the toggle condition for bit 2
1× AND: detect 5: Q2 AND Q0
1× OR: reset when CLR or the count is 5
3× AND: masking each D input with NOT (CLR OR count is 5)
2× NOT: NOT Q0 and the inverted reset

Step by step

Build a 3-bit synchronous counter: D0 = NOT Q0, D1 = Q1 XOR Q0, D2 = Q2 XOR (Q1 AND Q0), all three flip-flops on one clock.
Detect five: Q2 AND Q0. No other state from 0 to 5 has both bits set (4 is 100, 3 is 011).
OR that with CLR, invert it, and AND every next-state signal with the result. At 5 the next edge loads 000 instead of 110.
Probe Q0 to Q2, pulse CLR for one clock, and watch 000, 001, 010, 011, 100, 101, then back to 000.

Mod-6 counter sequence

Clock edge	Q2 Q1 Q0	Count
CLR	000	0
1	001	1
2	010	2
3	011	3
4	100	4
5	101	5
6	000	0

Six states, then repeat; the codes 110 and 111 are never reached after a clear. The same recipe makes any mod-N counter: count in binary, detect N - 1 with the AND of its 1 bits (when no smaller reachable state shares them), and load zero on the next edge. The decade counter is the mod-10 case. The run checks all three bits over 9 clocks, through the rollover.

You can also read the full theory in the lesson on counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the mod-6 counter in the lab →

Frequently asked

How do you design a mod-6 counter?

Use three flip-flops (2^3 = 8 is the smallest power of two that is at least 6). Count in binary and, when the count reaches 5 (101), force the next state to 000. Synchronously that means ANDing every next-state input with NOT (Q2 AND Q0).

How many flip-flops does a mod-6 counter need?

Three. Two flip-flops give only four states; three give eight, and the counter uses six of them.

What is the difference between a synchronous and an asynchronous mod-6 counter?

An asynchronous (ripple) mod-6 counter usually detects 6 (110) with Q2 AND Q1 and clears the flip-flops immediately, so 110 appears very briefly and can glitch. The synchronous version detects 5 and loads 000 on the next clock edge, so it never shows an invalid state.

Where is a mod-6 counter used?

In digital clocks for the tens digit of seconds and minutes (0 to 5), and anywhere a divide-by-6 is needed: its top bit completes one cycle every six clock pulses.