How to build a clocked SR flip-flop using NAND gates

A clocked SR flip-flop, also called a gated SR latch, is four NAND gates: two gate the S and R inputs with the clock, and two cross-coupled NANDs store the bit. While CLK is 1, S = 1 sets Q to 1 and R = 1 resets it to 0; while CLK is 0, the inputs are ignored and Q holds.

The cross-coupled pair on its own is the NAND SR latch, which has active-low inputs. The two gating NANDs fix both of its awkward points: they make S and R active-high (each NAND inverts), and they hold both latch inputs at 1, the latch's hold state, whenever CLK is 0. Strictly this is a level-triggered latch rather than an edge-triggered flip-flop, but many textbooks call it a clocked SR flip-flop. S = R = 1 while CLK is 1 is still forbidden: it drives both outputs to 1, and when CLK falls the result depends on which gate is faster. The D latch removes that case by deriving R from S. In the live circuit CLK and R start at 1, which resets Q to 0; CLK is an ordinary switch here, so you control exactly when the latch listens.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× NAND: gating: NAND(S, CLK) and NAND(R, CLK)
2× NAND: the cross-coupled latch that stores Q and Qbar

Step by step

Place inputs S, R and CLK, and probes Q and Qbar.
Gate the inputs: N1 = NAND(S, CLK) and N2 = NAND(R, CLK). With CLK = 0 both are 1 no matter what S and R do.
Cross-couple two NANDs: Q = NAND(N1, Qbar) and Qbar = NAND(N2, Q).
Set CLK = 1 and pulse S: Q goes to 1. Pulse R: Q goes to 0. Set CLK = 0 and change S and R: Q does not move.

Clocked SR flip-flop truth table

CLK	S	R	Q next	State
0	X	X	Q	hold (inputs ignored)
1	0	0	Q	hold
1	0	1	0	reset
1	1	0	1	set
1	1	1	1 (Q = Qbar)	invalid

Before the page is built the circuit is stepped through 8 input changes with its memory carried between steps: set, hold, a reset attempt with CLK = 0 (ignored), reset, a set attempt with CLK = 0 (ignored), set, hold and reset. Q and Qbar matched at every step. The invalid row is listed for completeness and is not part of the run.

You can also read the full theory in the lesson on the SR latch. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the SR flip-flop from NAND gates in the lab →

Frequently asked

How do you make an SR flip-flop using NAND gates?

Use four NAND gates. Two gate the inputs with the clock, N1 = NAND(S, CLK) and N2 = NAND(R, CLK), and two cross-coupled NANDs store the bit: Q = NAND(N1, Qbar), Qbar = NAND(N2, Q).

What is the difference between an SR latch and a clocked SR flip-flop?

The plain SR latch reacts to S and R at any moment. The clocked version adds an enable (CLK): it only responds while CLK is 1 and holds its state while CLK is 0.

Why is S = R = 1 not allowed?

With CLK = 1 it forces both outputs to 1, so Q and Qbar are no longer complements, and when CLK or the inputs return to 0 the latch falls into a state that depends on gate delays. The JK flip-flop turns this case into a toggle, and the D latch makes it impossible.

Is a gated SR latch edge-triggered?

No. It is level-triggered: it follows S and R for as long as CLK is 1. An edge-triggered SR flip-flop needs a master-slave pair or a dedicated edge-triggered design.