4-to-16 decoder: truth table and circuit, live

A 4-to-16 decoder turns a 4-bit number A3 A2 A1 A0 into one active output out of sixteen, Y0 to Y15. This one is built the way large decoders usually are: two 2-to-4 predecoders, one for A3 A2 and one for A1 A0, and 16 AND gates that each combine one line from each.

Output Yn is the AND of the four address bits, each taken as is or inverted to match n: Y13 (1101) is A3 AND A2 AND NOT A1 AND A0. Building each output as its own 4-input AND would take 48 two-input ANDs. Predecoding shares the work: the high pair A3 A2 has only four patterns and so does the low pair A1 A0, so each 2-to-4 decoder makes its four lines once, and every output is a single AND of one line from each. That brings the circuit down to 24 ANDs and 4 NOTs, and it is the same trick memory chips use to decode row addresses. A 4-to-16 decoder can also be made from two 3-to-8 decoders with enables, with A3 picking which one is on. All 16 addresses are checked before the page is built; the live circuit starts at 0000, so Y0 is lit.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

4× NOT: NOT A3, NOT A2, NOT A1 and NOT A0
4× AND: high predecoder: H0 to H3, the four combinations of A3 and A2
4× AND: low predecoder: L0 to L3, the four combinations of A1 and A0
16× AND: Yn = H(n div 4) AND L(n mod 4)

Step by step

Place inputs A3 to A0 and probes Y0 to Y15.
High predecoder: from A3, A2 and their inverses make H0 = A3' A2', H1 = A3' A2, H2 = A3 A2' and H3 = A3 A2.
Low predecoder: the same for A1 and A0, giving L0 to L3.
For each n from 0 to 15, AND H(n div 4) with L(n mod 4) to make Yn.
Count A3 A2 A1 A0 up from 0000: the lit output walks from Y0 to Y15.

4-to-16 decoder truth table

A3 A2 A1 A0	Active output
0000	Y0
0001	Y1
0010	Y2
0011	Y3
0100	Y4
0101	Y5
0110	Y6
0111	Y7
1000	Y8
1001	Y9
1010	Y10
1011	Y11
1100	Y12
1101	Y13
1110	Y14
1111	Y15

Exactly one output is 1 for every address and the other fifteen are 0. Add an enable input by ANDing it into the predecoders, and two such decoders with enables make a 5-to-32 decoder.

You can also read the full theory in the lesson on decoders. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 4-to-16 decoder in the lab →

Frequently asked

What is a 4 to 16 decoder?

A combinational circuit with 4 inputs and 16 outputs that sets to 1 exactly the output whose number is the binary input. It selects one of 16 memory locations, registers or devices.

How many gates does a 4-to-16 decoder need?

With predecoding, 4 NOT gates and 24 two-input ANDs: 8 in the two 2-to-4 predecoders and 16 for the outputs. With 4-input AND gates, 16 ANDs and 4 NOTs.

How do you make a 4-to-16 decoder from 3-to-8 decoders?

Use two 3-to-8 decoders with enable inputs. Feed A2 A1 A0 to both, enable the first with NOT A3 and the second with A3: the first covers Y0 to Y7, the second Y8 to Y15.

How do you make a 4-to-16 decoder from 2-to-4 decoders?

Use five 2-to-4 decoders with enables: one decodes A3 A2, and its four outputs enable the other four, which each decode A1 A0. This page's circuit is the same idea with the enables written as AND gates.