How to build a 4-bit carry-select adder from logic gates

A carry-select adder speeds up addition by computing the upper bits twice in parallel, once assuming the carry into them is 0 and once assuming it is 1, then picking the right result with multiplexers as soon as the real carry arrives. This 4-bit one ripples bits 0 and 1 from Cin and precomputes bits 2 and 3 both ways.

In a ripple-carry adder the carry crawls through every full adder in turn, so the top bit waits for all the others. Here the upper block does not wait: both of its versions start at once, and the only thing that depends on the lower block's carry c2 is a row of 2-to-1 multiplexers. The price is hardware, since the upper bits need two adders instead of one. Wide adders are split into several such blocks, and making each block a little larger than the one before keeps the delay growing roughly with the square root of the width instead of linearly. Compare the carry-lookahead adder, which instead computes every carry directly from generate and propagate signals. All 512 combinations of A, B and Cin are checked against real addition before the page is built.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× full adder: bits 0 and 1, rippling from Cin to the carry c2
2× full adder: bits 2 and 3 with the carry-in tied to 0 (GND)
2× full adder: bits 2 and 3 with the carry-in tied to 1 (VDD)
3× 2-to-1 mux: S2, S3 and Cout, selected by c2 (each mux is 2 AND and 1 OR)
1× NOT: NOT c2 for the multiplexers

Step by step

Place inputs A3 to A0, B3 to B0 and Cin, and probes S3 to S0 and Cout.
Lower block: two full adders ripple bits 0 and 1 from Cin, giving S0, S1 and the carry c2.
Upper block, twice: two full adders for bits 2 and 3 with the carry-in tied to 0 (GND), and two more with it tied to 1 (VDD).
Use c2 as the select of three 2-to-1 multiplexers that pick S2, S3 and Cout from the two upper blocks.
Try 0111 + 0001: the lower block makes c2 = 1, so the multiplexers take the carry-1 results and S = 1000.

Worked examples

A	B	Cin	c2	Upper block used	S	Cout
0011	0001	0	1	carry-in 1	0100	0
0100	0100	0	0	carry-in 0	1000	0
0111	0001	0	1	carry-in 1	1000	0
1001	0110	1	1	carry-in 1	0000	1
1111	0001	0	1	carry-in 1	0000	1

Each full adder here is two XOR, two AND and one OR gate, so the circuit has 40 gates; a 4-bit ripple-carry adder built the same way has 20. That doubling of the upper adders is the cost of not waiting for the carry.

You can also read the full theory in the lesson on faster adders and carry lookahead. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 4-bit carry-select adder in the lab →

Frequently asked

What is a carry select adder?

An adder that splits the bits into blocks and computes each upper block twice, for a carry-in of 0 and of 1, then uses multiplexers to select the correct result when the real carry arrives.

Is a carry select adder faster than a ripple carry adder?

Yes, for wide adders: the upper blocks add at the same time as the lower ones, so the carry passes through one multiplexer per block instead of one full adder per bit. It costs almost twice the adder hardware.

What is the difference between carry select and carry lookahead?

Carry lookahead computes each carry early from generate and propagate signals. Carry select does not compute the carry early at all: it prepares both possible results and chooses one.

What is the delay of a carry select adder?

With equal blocks of k bits, roughly k full-adder delays for the first block plus one multiplexer delay for each later block. Making each block slightly larger than the one before balances the two, so the delay grows about with the square root of the width.