CMOS XOR gate: twelve transistors, live

A static CMOS XOR gate uses twelve transistors: two inverters make NOT A and NOT B, and an eight-transistor complex gate pulls the output low when A and B are equal and high when they differ.

The pull-down network has two NMOS paths from Y to ground: A in series with B, and NOT A in series with NOT B. One of them conducts exactly when A = B, giving Y = 0. The pull-up network is its dual: PMOS on A and B in parallel, in series with PMOS on NOT A and NOT B in parallel. That path conducts when (NOT A OR NOT B) AND (A OR B), which is exactly A XOR B. XOR needs the inverted inputs because it is not monotonic: raising A can push the output up or down depending on B, and a single CMOS stage can only answer a rising input by pulling down. Twelve transistors is the textbook static version; a design with transmission gates gets XOR down to about eight. With ready-made gates, XOR is four NANDs, as in the XOR from NAND build, which is 16 transistors.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× CMOS inverter (1 PMOS + 1 NMOS): NOT A and NOT B
4× NMOS transistor: pull-down: (A series B) in parallel with (NOT A series NOT B)
4× PMOS transistor: pull-up: (A parallel B) in series with (NOT A parallel NOT B)

Step by step

Place VDD, GND, inputs A and B, and a probe Y.
Build two CMOS inverters to make NOT A and NOT B.
Pull-down: from Y to GND, one NMOS pair in series gated by A and B, and beside it a second series pair gated by NOT A and NOT B.
Pull-up: from VDD, two PMOS in parallel gated by A and B, then two more in parallel gated by NOT A and NOT B, ending at Y.
Check all four rows: Y is 1 only when exactly one input is 1.

CMOS XOR truth table, network by network

A	B	NMOS path on	PMOS path on	Y
0	0	NOT A, NOT B	none	0
0	1	none	A's, NOT B's	1
1	0	none	B's, NOT A's	1
1	1	A, B	none	0

In every row exactly one network has a complete path, so Y is never floating and never shorted. All four rows are checked on the live circuit, which is made of transistors only, before the page is built.

You can also read the full theory in the lesson on XOR at the transistor level. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the CMOS XOR gate in the lab →

Frequently asked

How many transistors are in a CMOS XOR gate?

Twelve in the standard static design: four for the two input inverters and eight for the complex gate. Transmission-gate designs use about eight, and an XOR made of four NAND gates uses 16.

Why does a CMOS XOR gate need inverted inputs?

XOR is not monotonic: raising one input can push the output either way, depending on the other input. A single CMOS stage can only answer a rising input by pulling its output down, so the gate needs both A and NOT A, and B and NOT B.

What Boolean functions do the two networks implement?

The pull-down conducts when A B + A' B' is 1 (the inputs are equal), pulling Y to 0. The pull-up conducts when (A + B)(A' + B') is 1, which equals A XOR B.

How is XNOR built in CMOS?

Either add an inverter after the XOR, or swap the pairing: a pull-down of (A series NOT B) in parallel with (NOT A series B) pulls the output low when the inputs differ, which gives XNOR in the same twelve transistors.