How to build a half subtractor using only NAND gates

A half subtractor can be built from five NAND gates: four of them form an XOR for the difference D = A XOR B, and the fifth inverts a signal the XOR already makes, giving the borrow Bout = NOT A AND B.

The XOR is the classic four-NAND arrangement: N1 = NAND(A, B), then N2 = NAND(A, N1) and N3 = NAND(B, N1), and D = NAND(N2, N3). The trick is N3. Since N1 = NOT (A AND B), N3 = NOT (B AND NOT (A AND B)) = NOT (NOT A AND B), which is exactly the inverted borrow, so one more NAND with both inputs tied to N3 gives Bout = NOT A AND B. Compare the half adder from NAND gates, which inverts N1 instead (NOT N1 = A AND B, the carry), and the half subtractor from XOR, AND and NOT. Two half subtractors and an OR make a full subtractor; the NAND-only version is the full subtractor from NAND gates.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

4× NAND: D = A XOR B: N1 = NAND(A, B), N2 = NAND(A, N1), N3 = NAND(B, N1), D = NAND(N2, N3)
1× NAND: Bout = NAND(N3, N3) = NOT N3 = NOT A AND B

Step by step

Place inputs A and B.
Build A XOR B from four NANDs: N1 = NAND(A, B), then NAND(A, N1) and NAND(B, N1), then NAND those two. That output is D.
Add a fifth NAND with both inputs on N3 = NAND(B, N1). Its output is Bout.
Probe D and Bout and try all four rows: only A = 0, B = 1 borrows.

Half subtractor truth table

A	B	D	Bout
0	0	0	0
0	1	1	1
1	0	1	0
1	1	0	0

The only row that borrows is A = 0, B = 1: 0 minus 1 has to borrow 2 from the next column, leaving 2 - 1 = 1 here, so D = 1 and Bout = 1. All four rows are checked on the live circuit before the page is built.

You can also read the full theory in the lesson on the half subtractor. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the half subtractor from NAND gates in the lab →

Frequently asked

How many NAND gates are needed for a half subtractor?

Five: four for the XOR that gives the difference, and one to invert the XOR's third gate into the borrow.

What is the difference between a NAND half adder and a NAND half subtractor?

Both use the same four-NAND XOR for the result bit. The adder's carry is NOT N1 = A AND B; the subtractor's borrow is NOT N3 = NOT A AND B. Same five gates, a different signal inverted.

What are the half subtractor equations?

D = A XOR B = A'B + AB' and Bout = A'B, where A' means NOT A.