Full adder using 4-to-1 multiplexers (MUX), live

A full adder can be built from two 4-to-1 multiplexers and one NOT gate. A and B drive the select lines of both muxes, so each mux picks one pair of rows of the truth table, and its data inputs, Cin, NOT Cin, 0 or 1, are read straight off that table.

For fixed A and B, each output of a full adder is one of only four functions of Cin: 0, 1, Cin or NOT Cin. The sum is Cin when A = B and NOT Cin when they differ, so the sum mux gets Cin, NOT Cin, NOT Cin, Cin on its inputs D0 to D3. The carry is 0 when A = B = 0, 1 when A = B = 1, and Cin otherwise, so the carry mux gets 0, Cin, Cin, 1. This is a general trick: any function of n variables fits in one 2^(n-1)-to-1 multiplexer, with n - 1 variables on the selects and the last one, its inverse, 0 or 1 on each data input. Each MUX block here is the 4-to-1 multiplexer from logic gates, saved as a part; open the circuit in the lab to look inside. Compare the gate-level full adder.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× 4-to-1 MUX: one for S and one for Cout, both with S1 = A and S0 = B
1× NOT: NOT Cin for the sum mux
2× constant: 0 (GND) and 1 (VDD) on the carry mux

Step by step

Place inputs A, B and Cin, two 4-to-1 multiplexers, and probes S and Cout.
Wire A to S1 and B to S0 on both multiplexers, so the select value is the row number A B.
Sum mux: D0 = Cin, D1 = NOT Cin, D2 = NOT Cin, D3 = Cin.
Carry mux: D0 = 0 (GND), D1 = Cin, D2 = Cin, D3 = 1 (VDD).
Check all eight rows: S and Cout match the full adder truth table.

Which input each mux selects

A B (select)	S gets	Cout gets
00	Cin	0
01	NOT Cin	Cin
10	NOT Cin	Cin
11	Cin	1

Expanding each row for Cin = 0 and Cin = 1 gives the usual eight-row full adder truth table; all eight rows are checked on the live circuit before the page is built.

You can also read the full theory in the lesson on the multiplexer as a universal block. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the full adder using 4:1 multiplexers in the lab →

Frequently asked

How do you implement a full adder using 4:1 multiplexers?

Use two 4-to-1 multiplexers with A and B on the select lines. The sum mux's data inputs are Cin, NOT Cin, NOT Cin, Cin and the carry mux's are 0, Cin, Cin, 1, read straight from the truth table.

How many multiplexers are needed for a full adder?

Two 4-to-1 multiplexers, one per output, plus a NOT gate for NOT Cin. With two 8-to-1 multiplexers you could put A, B and Cin all on the selects and wire each output's truth-table column to the data inputs as constants.

Can a half adder be built from multiplexers?

Yes, with A on the select of two 2-to-1 multiplexers: the sum mux passes B when A = 0 and NOT B when A = 1, and the carry mux passes 0 when A = 0 and B when A = 1.

Why build logic from multiplexers?

A multiplexer can implement any function of its select inputs, so one block type covers everything. FPGAs use the same idea: their lookup tables are multiplexers whose data inputs are programmable bits.