AND gate from transistors: CMOS NAND plus inverter, live

A CMOS AND gate takes six transistors: a four-transistor NAND gate followed by a two-transistor inverter. CMOS cannot make AND in one stage, because a single stage of complementary transistors always inverts.

The first stage is the CMOS NAND gate: two PMOS in parallel from VDD to an inner node X and two NMOS in series from X to ground, so X = NOT (A AND B). The second stage is a CMOS inverter on X, which turns it back into Y = A AND B. Why not one stage? An NMOS passes a strong 0 but only a weak 1, and a PMOS is the reverse, so a static CMOS stage always puts the PMOS on the supply side and the NMOS on the ground side. PMOS turn on when their input is 0, so raising an input can only pull such a stage's output down: every single-stage gate inverts. That is why NAND (4 transistors) is cheaper than AND (6), and why designers think in NAND and NOR. More in the pull-up and pull-down network lessons, or compare the CMOS OR gate.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× PMOS transistor: NAND stage pull-up: in parallel from VDD to X, gated by A and by B
2× NMOS transistor: NAND stage pull-down: in series from X to GND, gated by A and by B
1× PMOS transistor: inverter pull-up from VDD to Y, gated by X
1× NMOS transistor: inverter pull-down from Y to GND, gated by X

Step by step

Place VDD, GND, inputs A and B, and a probe Y.
Build the NAND stage: two PMOS side by side from VDD to a node X, one gated by A and one by B, and two NMOS in a stack from X to GND, gated by A and B.
Build an inverter on X: a PMOS from VDD to Y and an NMOS from Y to GND, both gated by X.
Try all four input pairs: X is 0 only for A = B = 1, so Y is 1 only then.

CMOS AND truth table, stage by stage

A	B	NAND PMOS on	NAND NMOS stack	X (NAND)	Y (AND)
0	0	both	open	1	0
0	1	A's	open	1	0
1	0	B's	open	1	0
1	1	none	closed	0	1

In each stage exactly one network conducts for every input, so X and Y are always driven, never floating and never shorted. All four rows are checked on the live circuit, which is made of transistors only, before the page is built.

You can also read the full theory in the lesson on the AND gate. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the CMOS AND gate in the lab →

Frequently asked

How many transistors are in an AND gate?

Six in CMOS: four for a NAND gate and two for the inverter after it. An n-input CMOS AND needs 2n + 2.

Why is a CMOS AND gate made from NAND and NOT?

A single static CMOS stage always inverts: its PMOS pull-up turns on for inputs at 0 and its NMOS pull-down for inputs at 1. So the natural one-stage gate is NAND, and AND adds an inverter.

Which is faster, NAND or AND?

NAND. An AND gate is the same NAND stage plus an inverter, so it costs two more transistors and one more gate delay. Logic is often designed directly in NAND form for that reason.

Can you make an AND gate with two transistors?

Yes, for a demo: two NMOS (or NPN) transistors in series from the supply to the output, with a resistor from the output to ground. The output rises only when both are on, but its 1 is weak and the resistor wastes power while it conducts, which is why CMOS uses six transistors.