Serial adder: add two numbers one bit per clock, live

A serial adder adds two binary numbers one bit per clock, least significant bit first, using a single full adder and a D flip-flop that remembers the carry for the next bit. This one also registers each sum bit in a second flip-flop, so S shows the result bit of the clock that just passed.

A parallel (ripple-carry) adder needs one full adder per bit and gives the whole sum at once. A serial adder trades time for hardware: n clocks for an n-bit sum, but the same small circuit for any width. In a complete design, shift registers feed A and B in one bit at a time and collect the sum bits, as in the shift register build; here A and B are switches that are sampled on every clock edge. CLR is synchronous: with CLR on, the next clock clears both the carry and the sum. Two additions are checked over 11 clocks before the page is built: 6 + 7 = 13, and 15 + 1 = 16, where the final carry comes out as a fifth sum bit. The live circuit starts with CLR on.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× XOR: sum = A XOR B XOR C
2× AND: the carry terms A AND B and (A XOR B) AND C
1× OR: the carry out of this bit
2× D flip-flop: C holds the carry for the next bit; S registers the sum bit
1× NOT: NOT CLR
2× AND: synchronous clear: each flip-flop's D ANDed with NOT CLR

Step by step

Place a clock CLK, inputs CLR, A and B, and probes S and C.
Build a full adder from A, B and the carry flip-flop's output C: sum = A XOR B XOR C, carry = (A AND B) OR ((A XOR B) AND C).
Feed the carry into one D flip-flop (C) and the sum into another (S), each through an AND with NOT CLR.
Clear with CLR, then present the bits of both numbers, least significant first, one pair per clock, and read one sum bit from S after each clock.

6 + 7, one bit per clock

Clock	A bit	B bit	Carry in	S	Carry out (C)
1	0	1	0	1	0
2	1	1	0	0	1
3	1	1	1	1	1
4	0	0	1	1	0

Reading S from the first clock to the last gives 1, 0, 1, 1, which is 1101 written least significant bit first: 13. A fifth clock with A = B = 0 would emit any remaining carry, which is how 15 + 1 produces 10000 in the checked sequence.

You can also read the full theory in the lesson on the full adder. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the serial adder in the lab →

Frequently asked

What is a serial adder?

An adder that adds two numbers one bit per clock cycle, least significant bit first, with one full adder and a flip-flop that keeps the carry from each bit for the next.

What is the difference between a serial adder and a parallel adder?

A parallel adder has one full adder per bit and produces all the sum bits in one step. A serial adder reuses one full adder over n clocks, so it is smaller but n times slower.

Why does a serial adder need a flip-flop?

The carry out of one bit must be added into the next bit, which arrives on the next clock. The D flip-flop stores it for exactly that one clock.

Is a serial adder a Mealy or a Moore machine?

With the sum taken straight from the full adder, it is a Mealy machine: the output depends on the inputs and the stored carry. This version registers the sum in a flip-flop, so its outputs change only on clock edges, like a Moore machine's.