RARS alternative: from RISC-V assembly to the hardware below it
RARS, the RISC-V Assembler and Runtime Simulator, assembles and simulates RISC-V assembly language programs, and its README gives its primary goal as being an effective development environment for people getting started with RISC-V. It supports the RISC-V IMFDN base in both riscv32 and riscv64, system calls that match the behaviour of MARS or SPIKE, debugging with breakpoints or ebreak, a side-by-side view from each pseudo-instruction to its machine code, and multifile assembly. It is distributed as an executable jar that needs Java 8 or later. RARS was built on MARS 4.5, the MIPS assembler and simulator, keeps MARS's permissive MIT-style license, and its latest stable release on GitHub is version 1.6, from February 2023. RARS runs your RISC-V program on a processor you never see inside; digiwleea has you build a processor's hardware yourself, gate by gate.
What RARS is good at
A complete RISC-V assembly environment in one download: write, assemble and debug programs with breakpoints, see how each pseudo-instruction expands into real instructions, and call the system for input and output much as in MARS, so a course moving from MIPS to RISC-V keeps a familiar tool. If you cannot install Java, Venus runs RV32IM assembly in the browser, and Ripes animates a processor's datapath and caches as the program runs. (digiwleea is an independent project, not affiliated with RARS or its authors.)
How digiwleea is different
digiwleea does not run RISC-V. It covers the hardware below the instruction set: in the browser you build NOT and NAND from CMOS transistors, then adders, an ALU, a register file, RAM, a program counter and a control unit, through a 40+ level course where every part is checked against its truth table, with an AI tutor (Wleea). The CPU you finish with is a small 8-bit accumulator machine whose capstone runs a stored LOAD, ADD, STORE, HALT program, much simpler than RISC-V but built entirely by you. Use RARS for the assembly course and digiwleea to see what a processor does with each instruction.
| RARS | digiwleea | |
|---|---|---|
| You work with | RISC-V assembly (riscv32 and riscv64, IMFDN) | Transistors, gates and wires you place |
| Runs in | Java 8 or later (executable jar) | Any modern browser |
| Debugging | Breakpoints and ebreak | Live values on every wire, waveform view |
| The processor | Simulated, not shown inside | Built by you: ALU, registers, RAM, control |
| Price | Free, open source (MIT-style license) | Free lab and Act I; Premium for the full course |
No sign-up is needed to start: open the lab and place your first transistor, or read the free theory course. The account (and the AI tutor) are optional.
More comparisons: CPU and assembly simulators
See for yourself: build a logic gate from transistors in the simulator, then follow the path from sand to an 8-bit CPU.
Open the digiwleea lab →Frequently asked
What is RARS?
RARS, the RISC-V Assembler and Runtime Simulator, is a free Java program that assembles and simulates RISC-V assembly, made for people getting started with RISC-V. It is built on MARS 4.5, the MIPS simulator.
How do I download and run RARS?
RARS is distributed as an executable jar file on its GitHub releases page; the latest stable release is version 1.6. It needs Java 8 or later, and you start it by opening the jar.
Can I run RARS in a browser?
No, RARS is a Java desktop application. For RISC-V assembly in the browser, Venus runs RV32IM programs, and Ripes has an experimental web version.
What is the difference between RARS and MARS?
MARS simulates MIPS; RARS was built on MARS 4.5 and simulates RISC-V instead. It removed MIPS-specific behaviour such as delayed branching and a few tools, and added a framework that tests compatibility with the RISC-V specification.