Venus RISC-V simulator alternative: build the processor yourself

Venus is a free, open-source (MIT) RISC-V instruction set simulator built for education. It runs in the browser: you write RV32IM assembly, then step through it one instruction at a time (with an undo button to step back), set breakpoints, see each instruction's machine code beside your source, and watch the registers and a visualization of memory. It supports several environment calls, including print and sbrk. The original version is by kvakil at kvakil.github.io/venus; a maintained fork by ThaumicMekanism adds a basic package system and a Java version alongside the web one. Venus runs RISC-V programs on a processor you never see inside; digiwleea has you build a processor's hardware yourself, gate by gate.

What Venus is good at

Learning RISC-V assembly with nothing to install: the editor, the simulator and the debugger are one web page, and stepping backward with undo makes it easy to see exactly what an instruction changed. For a course built on RISC-V, it is a quick, focused companion; Ripes adds pipeline and cache views if you need them. (digiwleea is an independent project, not affiliated with Venus or its authors.)

How digiwleea is different

digiwleea does not run RISC-V. It covers the hardware below the instruction set: in the browser you build NOT and NAND from CMOS transistors, then adders, an ALU, a register file, RAM, a program counter and a control unit, through a 40+ level course where every part is checked against its truth table, with an AI tutor (Wleea). The CPU you finish with is a small 8-bit accumulator machine whose capstone runs a stored LOAD, ADD, STORE, HALT program, much simpler than RV32IM but built entirely by you.

	Venus	digiwleea
Focus	RISC-V (RV32IM) assembly	Digital logic from transistors to a simple CPU
The CPU	Simulated RISC-V, not shown inside	Built by you: an 8-bit accumulator machine
Debugging	Step with undo, breakpoints, memory view	Probe any wire, step the clock, truth-table checks
Runs on	Browser (and a Java version in the fork)	Any modern browser
Price	Free, MIT license	Free lab and Act I; Premium for the full course

No sign-up is needed to start: open the lab and place your first transistor, or read the free theory course. The account (and the AI tutor) are optional.

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See for yourself: build a logic gate from transistors in the simulator, then follow the path from sand to an 8-bit CPU.

Open the digiwleea lab →

Frequently asked

What is the Venus RISC-V simulator?

Venus is a free, open-source RISC-V instruction set simulator for education that runs in the browser. It supports RV32IM, single-step debugging with undo, breakpoints and memory visualization.

What is the difference between Venus and Ripes?

Both run RISC-V in a visual simulator. Venus focuses on assembly and debugging in a web page; Ripes adds processor models with pipelines and caches, and runs on the desktop with an experimental browser version.

Can I see how a RISC-V register file is built?

digiwleea's register file page builds a small register file from flip-flops and multiplexers and runs it live; its course goes on to an 8-bit CPU you assemble yourself.