How a register file works: four 4-bit registers, live

A register file is the small, fast set of registers inside a CPU, with ports to write one register and read another. This live one holds four 4-bit registers: a write address WA1 WA0 and a write enable WE pick the register that loads D3 to D0 on the clock edge, and a read address RA1 RA0 picks the register whose contents appear on Q3 to Q0.

It is built from three parts you can try on their own. The write side is a 2-to-4 decoder with an enable: WE AND the decoded write address drives the load input of exactly one register, so only that register changes on the next rising edge of CLK while the other three keep their values. Each register is the 4-bit register with load, four D flip-flops that either reload their own outputs or take new data. The read side is four 4-to-1 multiplexers, one per bit, all steered by the read address. Reading needs no clock: change RA and Q changes at once. Real processors use the same structure with more and wider registers, and usually two read ports, so an instruction can read both of its operands while it writes its result; in this site's course the CPU's registers feed the ALU the same way. Here CLK is a plain switch. The circuit opens with WE = 1, so you can write register 0 straight away: set D, turn CLK on, then change RA to read the registers back. The registers start unknown until they are written, as in real hardware. Before the page is built, the 4-bit register is checked on its own (load, hold, load) and the register file through a 27-step sequence: four writes, four reads, an overwrite, and a write with WE = 0 that must change nothing.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

4× 4-bit register with load: registers R0 to R3, each four D flip-flops and a load multiplexer per bit
2× NOT + 4 AND: the 2-to-4 decode of the write address WA1 WA0
4× AND: each decoded line AND WE, the load signal of one register
4× 4-to-1 MUX: the read port: bit i of R0 to R3, selected by RA1 RA0, onto Qi

Step by step

Place inputs D3 to D0, WA1, WA0, WE, CLK, RA1, RA0 and probes Q3 to Q0.
Place four 4-bit registers with load, all on CLK, all with D3 to D0 as their data inputs.
Decode WA1 WA0 into four lines, AND each with WE, and wire line k to the load input of register k.
For each bit i, a 4-to-1 multiplexer chooses bit i of register RA1 RA0 and drives Qi.
Write a value: set WA and D, keep WE = 1, pulse CLK. Then set RA to the same address and read it back.

Ports and what they do

Inputs	When	What happens
WA1 WA0, D3..D0, WE = 1	rising edge of CLK	Register WA loads D; the other three keep their values
WE = 0	rising edge of CLK	No register changes
RA1 RA0	any time	Q3..Q0 show register RA at once (no clock needed)

The checked sequence

Step	Operation	Result
1 to 4	Write R0 = 0011, R1 = 0101, R2 = 1001, R3 = 1110	One register loads per clock
5 to 8	Read RA = 0, 1, 2, 3	Q shows 0011, 0101, 1001, 1110
9	Write R2 = 0110	Reading R2 shows 0110; R1 still shows 0101
10	Write 1111 to R1 with WE = 0	R1 still reads 0101, R3 still 1110

Reading is combinational and writing is clocked, which is why a CPU can read registers early in an instruction and write the result at the clock edge that ends it. Widen every register to 8 bits and you have the register file of an 8-bit processor; add more registers and the decoder and multiplexers grow with them.

You can also read the full theory in the lesson on the register file. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the register file (4 x 4-bit) in the lab →

Frequently asked

What is a register file?

The set of general-purpose registers inside a CPU, organized like a tiny, very fast memory: an address chooses which register is written on a clock edge, and other addresses choose which registers are read. This one has four 4-bit registers, one write port and one read port.

How does a register file work?

A decoder turns the write address into one load signal, gated by a write enable, so only that register captures the data on the clock edge. Multiplexers, one per bit, turn the read address into a selection of one register's outputs, with no clock needed for reading.

How many read and write ports does a register file have?

It depends on the processor. A typical RISC design reads two registers and writes one in each instruction, so it has two read ports and one write port; a read port is just another set of multiplexers. This example has one of each to keep it small.

What is the difference between a register file and RAM?

Both store words at addresses, but a register file is tiny and built from flip-flops right next to the ALU, with several ports that work in the same cycle. RAM is much larger, denser and slower, and usually has one port.