Master-slave JK flip-flop from NAND gates, live

A master-slave JK flip-flop is two clocked NAND latches in a row: the master follows J and K while the clock is 1, and the slave copies the master when the clock falls to 0. Because the output only changes after the master has stopped listening, J = K = 1 toggles exactly once per clock instead of racing.

A single clocked JK latch made of four NAND gates has a flaw. Its inputs are gated with its own outputs (J with NOT Q, K with Q), so with J = K = 1 and the clock held high, the output toggles, the new output re-enables the opposite input, and it toggles again, over and over for as long as the clock stays high. That is the race-around condition. The master-slave form breaks the loop: the master's input gates still use the slave's Q and NOT Q, but the slave only changes when the clock goes low, after the master has stopped listening, so each clock gives one decision. This build is the textbook eight NAND gates, with each 3-input NAND made of an AND feeding a NAND, plus a clock inverter and a clear (CLR). While CLR is on, Q is held at 0 whatever J does; the master keeps sampling J and K, so the first falling edge after CLR is released applies them as usual. Compare the JK flip-flop built on a D flip-flop and the clocked SR flip-flop from NAND gates, which is one half of this circuit.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× NAND (3-input): master input gates: NAND(J, CLK, NOT Q) and NAND(K, CLK, Q), each an AND then a NAND
2× NAND: the master latch, cross-coupled (one of them also takes CLR through an AND)
2× NAND: slave input gates, enabled by NOT CLK (the set gate also takes NOT CLR, through an AND)
2× NAND: the slave latch, giving Q and Qbar (Qbar also takes CLR through an AND)
2× NOT: NOT CLK for the slave and NOT CLR for the clear

Step by step

Place a clock CLK, inputs J, K and CLR, and probes Q and Qbar.
Master input gates: NAND J with CLK and Qbar, and NAND K with CLK and Q. Feeding back Q and Qbar is what makes J = K = 1 toggle.
Master latch: cross-couple two NANDs, one fed by the J gate and one by the K gate.
Slave: two more NANDs pass the master's outputs only when NOT CLK is 1, into a second cross-coupled pair that drives Q and Qbar.
Clear: with CLR on, Q = 0. Turn CLR off, then set J and K and watch Q change each time the clock falls.

JK truth table (on the falling clock edge)

J	K	Q next	Action
0	0	Q	hold
0	1	0	reset
1	0	1	set
1	1	NOT Q	toggle

Before the page is built, Q and Qbar are checked at every one of 13 clocks: a clear held for two clocks, with J = 1 during the first (Q stays 0), then hold, set, hold, reset, hold, three toggles in a row (one change per clock, no race-around), hold and reset. The live circuit starts with CLR on.

You can also read the full theory in the lesson on the JK flip-flop. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

half adder full adder half subtractor full subtractor 2:1 multiplexer 4:1 multiplexer XOR gate from NAND gates 2-to-4 decoder SR latch D flip-flop JK flip-flop T flip-flop 4-bit shift register 4-bit ripple carry adder D latch 1-to-4 demultiplexer 4-bit magnitude comparator 4-bit ring counter 4-bit Johnson counter 4-to-2 priority encoder 4-bit synchronous counter 3-to-8 decoder 8-to-1 multiplexer 4-bit carry lookahead adder half adder from NAND gates 2-bit comparator BCD to 7-segment decoder 4-bit up/down counter decade counter 2-bit multiplier 4-bit ALU 4-bit array multiplier NOT, AND, OR and NOR from NAND NOT, OR, AND and XOR from NOR full adder from NAND gates SR latch from NAND gates parity generator and checker 4-bit adder/subtractor BCD adder 4-bit universal shift register mod-6 counter 4-bit ripple counter binary to Gray code converter half adder from NOR gates full adder from NOR gates 4-bit register with parallel load 1011 sequence detector binary to BCD converter D flip-flop from NAND gates 1-bit ALU CMOS inverter CMOS NAND gate CMOS NOR gate PISO shift register SR flip-flop from NAND gates BCD to excess-3 code converter Hamming (7,4) code encoder and corrector traffic light controller 4-bit barrel shifter CMOS AND gate CMOS OR gate CMOS XOR gate 1-bit magnitude comparator half subtractor from NAND gates full subtractor from NAND gates 8-to-3 encoder Gray to binary converter 4-to-16 decoder full adder using 4:1 multiplexers edge detector serial adder 4-bit carry-select adder Mealy machine (1011 detector)half subtractor from NOR gates 1-to-8 demultiplexer excess-3 to BCD code converter vending machine FSM 4-bit carry-save adder 3-bit synchronous counter (JK)CMOS transmission gate tri-state buffer (CMOS)2-to-1 mux from transmission gates

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the master-slave JK flip-flop (NAND) in the lab →

Frequently asked

What is a master-slave JK flip-flop?

Two latches in series on opposite clock phases: the master captures J and K while the clock is high, and the slave passes the master's state to the output when the clock goes low. The output therefore changes once per clock, on the falling edge.

What is the race-around condition?

In a level-triggered JK latch with J = K = 1, the output toggles, the toggled output feeds back to the inputs, and it toggles again, repeatedly, for as long as the clock is high. The final value then depends on how long the clock pulse lasts. A master-slave or an edge-triggered design avoids it.

How many NAND gates are in a master-slave JK flip-flop?

Eight in the textbook circuit: two 3-input NANDs and two 2-input NANDs for the master, four 2-input NANDs for the slave, plus an inverter for the clock. With only 2-input gates, each 3-input NAND becomes an AND followed by a NAND, as here.

Is a master-slave flip-flop edge-triggered?

It behaves like one from the outside, since the output changes only when the clock falls. Inside, the master is level-sensitive, so a pure master-slave JK can catch a glitch on J or K that happens while the clock is high (ones catching). Edge-triggered designs do not have that weakness.