3-bit synchronous counter using JK flip-flops, live

A 3-bit synchronous counter counts 0 to 7 and wraps, with all three flip-flops on one clock. With JK flip-flops the design is J0 = K0 = 1, J1 = K1 = Q0 and J2 = K2 = Q1 AND Q0: each bit toggles exactly when all the bits below it are 1.

This is the textbook design procedure in miniature: write the state table (000, 001, up to 111 and back to 000), look up the J and K each flip-flop needs in the JK excitation table, and simplify with K-maps. Every bit only ever holds or toggles, so J = K for each stage, and the toggle condition is the AND of the lower bits. The flip-flops are the master-slave JK flip-flops from NAND gates, saved as a part, so the count changes when the clock falls. The 4-bit synchronous counter uses D flip-flops instead, and a ripple counter chains the clocks instead of sharing one. Fourteen clocks are checked before the page is built, including the 7 to 0 wrap and a clear. The live circuit starts with CLR on: turn it off to count.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

3× JK flip-flop: one per bit, all on the same clock and the same CLR (each is the 8-NAND master-slave circuit)
1× AND: J2 = K2 = Q1 AND Q0
1× constant: J0 = K0 = 1 (VDD)

Step by step

Write the state table: each count and the one after it, 000 to 001 up to 111 to 000.
For each bit, use the JK excitation table: 0 to 0 needs J = 0, 0 to 1 needs J = 1, 1 to 0 needs K = 1, 1 to 1 needs K = 0 (the other input is a don't-care).
Simplify: J0 = K0 = 1, J1 = K1 = Q0, J2 = K2 = Q1 Q0.
Wire three JK flip-flops to one clock and one CLR, tie J0 and K0 to 1, feed Q0 to J1 and K1, and an AND of Q1 and Q0 to J2 and K2.
Turn CLR off: Q2 Q1 Q0 counts 000, 001, 010 up to 111 and wraps.

Count sequence and JK inputs

Count	Q2 Q1 Q0	J2 = K2	J1 = K1	J0 = K0
0	000	0	0	1
1	001	0	1	1
2	010	0	0	1
3	011	1	1	1
4	100	0	0	1
5	101	0	1	1
6	110	0	0	1
7	111	1	1	1

A 1 in a J = K column means that bit toggles on the next falling clock edge. From 111 every bit toggles at once, which is the wrap to 000.

You can also read the full theory in the lesson on synchronous counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 3-bit synchronous counter (JK) in the lab →

Frequently asked

How do you design a 3-bit synchronous counter?

Write the count sequence as a state table, find the J and K (or T, or D) inputs each flip-flop needs from its excitation table, simplify them with K-maps, and connect all flip-flops to one clock. With JK flip-flops: J0 = K0 = 1, J1 = K1 = Q0, J2 = K2 = Q1 Q0.

How many flip-flops does a 3-bit counter need?

Three. With n flip-flops a binary counter has 2 to the n states, so three give the eight counts 0 to 7 (a mod-8 counter).

What is the difference between a synchronous and an asynchronous counter?

In a synchronous counter every flip-flop shares one clock and all bits change together. In an asynchronous (ripple) counter each flip-flop is clocked by the previous one, so the change ripples through and the bits settle one after another.

How do you make it count down?

Toggle a bit when all lower bits are 0 instead of 1: J1 = K1 = NOT Q0 and J2 = K2 = NOT Q1 AND NOT Q0.