4-to-1 multiplexer using 2-to-1 multiplexers, live

A 4-to-1 multiplexer can be built from three 2-to-1 multiplexers in a tree: two muxes on the first level use S0 to pick D0 or D1 and D2 or D3, and a third mux uses S1 to pick between their outputs. The output is Y = D(S1 S0), exactly like a single 4-to-1 mux.

The select bits split the job: the low bit S0 chooses within each pair of inputs and the high bit S1 chooses which pair wins. The same trick scales: an 8-to-1 mux is two 4-to-1 muxes plus one 2-to-1 mux on S2, or seven 2-to-1 muxes in three levels, and in general a 2^n-to-1 mux takes 2^n - 1 two-input muxes. Each MUX block here is the gate-level 2-to-1 multiplexer saved as a part; open the circuit in the lab to look inside. Compare the flat 4-to-1 multiplexer from AND and OR gates and the 8-to-1 multiplexer. All 64 combinations of data and select inputs are checked before the page is built.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× 2-to-1 MUX: first level: D0 or D1, and D2 or D3, both selected by S0
1× 2-to-1 MUX: second level: the two results, selected by S1

Step by step

Place inputs D0 to D3, S1 and S0, three 2-to-1 multiplexers, and a probe Y.
First mux: D0 and D1 with select S0. Second mux: D2 and D3 with select S0.
Third mux: the outputs of the first two, with select S1. Its output is Y.
Set a pattern on D0 to D3 and count S1 S0 from 00 to 11: Y shows D0, D1, D2, D3 in turn.

4-to-1 multiplexer truth table

S1	S0	First level picks	Y
0	0	D0 (and D2)	D0
0	1	D1 (and D3)	D1
1	0	D0 (and D2)	D2
1	1	D1 (and D3)	D3

Both first-level muxes switch together on S0; S1 only decides which of their two outputs reaches Y.

You can also read the full theory in the lesson on the multiplexer. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

half adder full adder half subtractor full subtractor 2:1 multiplexer 4:1 multiplexer XOR gate from NAND gates 2-to-4 decoder SR latch D flip-flop JK flip-flop T flip-flop 4-bit shift register 4-bit ripple carry adder D latch 1-to-4 demultiplexer 4-bit magnitude comparator 4-bit ring counter 4-bit Johnson counter 4-to-2 priority encoder 4-bit synchronous counter 3-to-8 decoder 8-to-1 multiplexer 4-bit carry lookahead adder half adder from NAND gates 2-bit comparator BCD to 7-segment decoder 4-bit up/down counter decade counter 2-bit multiplier 4-bit ALU 4-bit array multiplier NOT, AND, OR and NOR from NAND NOT, OR, AND and XOR from NOR full adder from NAND gates SR latch from NAND gates parity generator and checker 4-bit adder/subtractor BCD adder 4-bit universal shift register mod-6 counter 4-bit ripple counter binary to Gray code converter half adder from NOR gates full adder from NOR gates 4-bit register with parallel load 1011 sequence detector binary to BCD converter D flip-flop from NAND gates 1-bit ALU CMOS inverter CMOS NAND gate CMOS NOR gate PISO shift register SR flip-flop from NAND gates BCD to excess-3 code converter Hamming (7,4) code encoder and corrector traffic light controller 4-bit barrel shifter CMOS AND gate CMOS OR gate CMOS XOR gate 1-bit magnitude comparator half subtractor from NAND gates full subtractor from NAND gates 8-to-3 encoder Gray to binary converter 4-to-16 decoder full adder using 4:1 multiplexers edge detector serial adder 4-bit carry-select adder Mealy machine (1011 detector)master-slave JK flip-flop (NAND)half subtractor from NOR gates 1-to-8 demultiplexer excess-3 to BCD code converter vending machine FSM 4-bit carry-save adder 3-bit synchronous counter (JK)CMOS transmission gate tri-state buffer (CMOS)2-to-1 mux from transmission gates mod-5 counter flip-flop conversion (JK to D)8-bit ALU decimal to BCD encoder BCD to decimal decoder XOR gate from NOR gates

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 4-to-1 mux from 2-to-1 muxes in the lab →

Frequently asked

How many 2-to-1 muxes make a 4-to-1 mux?

Three: two on the first level, selected by S0, and one on the second level, selected by S1.

How do you build an 8-to-1 mux from 4-to-1 muxes?

Use two 4-to-1 muxes for D0 to D3 and D4 to D7, both selected by S1 S0, and one 2-to-1 mux on S2 to pick between them.

How many 2-to-1 muxes make an 8-to-1 mux?

Seven, in three levels of four, two and one. A 2^n-to-1 mux always takes 2^n - 1 two-input muxes.

Is a mux tree slower than a single multiplexer?

Each level adds a mux delay, so a tree of n levels is slower than one flat n-select mux of AND and OR gates, but it is easy to build from standard parts and to extend.