Mod-5 counter: designed from its state table, live

A mod-5 counter counts 0, 1, 2, 3, 4 and back to 0, so it has five states and needs three flip-flops. Designed from its state table with the three unused states as don't-cares, it needs just three gates: D2 = Q1 AND Q0, D1 = Q1 XOR Q0 and D0 = NOR(Q2, Q0).

Three flip-flops have eight states and a mod-5 counter uses only five, so the next state of 101, 110 and 111 can be anything, which shrinks the K-maps. Don't-cares need one check, though: if noise ever drops the counter into an unused state, does it find its way back? Here it does: 101 and 110 go to 010, and 111 goes to 100, so the counter is self-starting. The mod-6 counter takes the other common approach, counting in binary and loading 0 after the last state, and the decade counter is the mod-10 version. A mod-5 counter also divides a clock frequency by 5. CLR is synchronous, and the live circuit starts with CLR on: turn it off to count.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

3× D flip-flop: the state Q2 Q1 Q0, on one clock
1× AND: D2 = Q1 AND Q0
1× XOR: D1 = Q1 XOR Q0
1× NOR: D0 = NOR(Q2, Q0)
1× NOT: NOT CLR
3× AND: synchronous clear: each D ANDed with NOT CLR

Step by step

Write the state table for 0 to 4 and back to 0, and mark the next state of 101, 110 and 111 as don't-cares.
Read a K-map for each flip-flop input: D2 = Q1 Q0, D1 = Q1 XOR Q0, D0 = Q2' Q0', which is NOR(Q2, Q0).
Check the unused states: each leads back into the count, so the counter is self-starting.
Wire three D flip-flops to one clock, add the three gates and a synchronous clear, and probe Q2 Q1 Q0.
Turn CLR off: the count runs 000, 001, 010, 011, 100 and wraps to 000.

State table, including the unused states

Q2 Q1 Q0	Count	Next state
000	0	001
001	1	010
010	2	011
011	3	100
100	4	000
101	unused	010
110	unused	010
111	unused	100

Before the page is built the counter is checked at every one of 14 clocks: a clear, the count with its 4 to 0 wrap, and a second clear partway through.

You can also read the full theory in the lesson on synchronous counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the mod-5 counter in the lab →

Frequently asked

What is a mod-5 counter?

A counter with five states, 0 to 4, that returns to 0 after 4. It is also called a divide-by-5 counter, because its outputs repeat once every five clock cycles.

How many flip-flops does a mod-5 counter need?

Three. Two flip-flops give only four states, and three give eight, of which a mod-5 counter uses five.

How do you make a mod-3 counter?

With two flip-flops counting 00, 01, 10: D1 = Q0 and D0 = NOR(Q1, Q0). The unused state 11 goes to 10, so it is self-starting too.

What does self-starting mean for a counter?

That from any unused state the counter reaches its normal sequence within a few clocks, so a glitch or power-up into a bad state cannot trap it there.