Tri-state buffer from transistors: 0, 1 or Z, live

A tri-state buffer passes its input A to its output Y when the enable EN is 1, and disconnects the output, leaving it floating in the high-impedance state Z, when EN is 0. This CMOS version uses eight transistors: an inverter on A, an inverter on EN, and a tri-state inverter of four transistors stacked between VDD and GND.

The tri-state inverter is the heart of it: two PMOS in series from VDD to Y, gated by NOT EN and NOT A, and two NMOS in series from Y to GND, gated by NOT A and EN. With EN = 0 the outer transistor of each stack is off, so neither network can reach Y. With EN = 1 both outer transistors are on and the inner pair works as an ordinary inverter on NOT A, so Y = A. Unlike a transmission gate, which only connects two wires, a tri-state buffer drives Y from the supply rails, so it restores a weak signal. That is why buses use tri-state drivers: many share one wire and the control logic enables exactly one at a time; two enabled at once with different values would connect VDD to GND. Read more in the tri-state lesson and on buses.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× transistor (CMOS inverter): NOT A
2× transistor (CMOS inverter): NOT EN
2× PMOS transistor: in series from VDD to Y, gated by NOT EN and NOT A
2× NMOS transistor: in series from Y to GND, gated by NOT A and EN

Step by step

Place VDD, GND, inputs A and EN, and a probe Y.
Build two CMOS inverters, for NOT A and NOT EN.
Pull-up: two PMOS in series from VDD to Y, the outer one gated by NOT EN and the inner one by NOT A.
Pull-down: two NMOS in series from Y to GND, the inner one gated by NOT A and the outer one by EN.
With EN = 1, Y follows A. With EN = 0, Y floats (Z).

Tri-state buffer truth table

EN	A	PMOS stack	NMOS stack	Y
0	0	off	off	Z (floating)
0	1	off	off	Z (floating)
1	0	off	on	0
1	1	on	off	1

All four rows, including the two floating ones, are checked on the live circuit, which is made of transistors only, before the page is built. It starts with A = 1 and EN = 0, so Y floats until you turn EN on.

You can also read the full theory in the lesson on tri-state buffers. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the tri-state buffer (CMOS) in the lab →

Frequently asked

What is a tri-state buffer?

A buffer with an enable input: when enabled, its output copies its input; when disabled, its output is disconnected and floats in the high-impedance state Z, so other drivers can use the same wire.

What does high impedance (Z) mean?

The output is neither pulled to 1 nor to 0; it is effectively disconnected, so whatever else drives the wire decides its value.

Why are tri-state buffers used on buses?

Many devices share one bus wire. Each drives it through a tri-state buffer, and the control logic enables one at a time, so exactly one device drives the bus and the rest stay disconnected.

What is the difference between a tri-state buffer and a transmission gate?

Both can disconnect their output. A transmission gate only connects or disconnects two wires and passes the input's strength along; a tri-state buffer drives its output from the supply rails, so it restores the signal.

What happens if two tri-state buffers drive a bus at once?

If they drive different values, one pulls the wire up while the other pulls it down: a short from VDD to GND, called bus contention. The control logic must enable only one at a time.