How to build a 1-to-8 demultiplexer from logic gates

A 1-to-8 demultiplexer sends one data input D to one of eight outputs, Y0 to Y7, chosen by the 3-bit select S2 S1 S0, and holds every other output at 0. Each output is D ANDed with the decoding of its own number: Y5 = D AND S2 AND NOT S1 AND S0.

It is a 3-to-8 decoder with D ANDed into every output, and the reverse of an 8-to-1 multiplexer. To save gates this one predecodes: four ANDs decode S1 S0 once, two more combine D with S2 and NOT S2, and each output ANDs one line from each group. The smallest demultiplexer, 1-to-2, is just Y0 = D AND NOT S and Y1 = D AND S, and the 1-to-4 demultiplexer sits in between. All 16 combinations of D and the select are checked before the page is built.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

3× NOT: NOT S2, NOT S1 and NOT S0
4× AND: decode S1 S0 into four lines
2× AND: D AND NOT S2, D AND S2
8× AND: Yi = (the D line for S2) AND (the line for S1 S0)

Step by step

Place inputs D, S2, S1 and S0 and probes Y0 to Y7.
Decode S1 S0 with two NOT gates and four ANDs into four lines, one per value 00 to 11.
AND D with NOT S2 and with S2 to get two lines, one for each half of the outputs.
For each output i, AND the S2 line for i div 4 with the S1 S0 line for i mod 4.
Turn D on and count S2 S1 S0 from 000 to 111: the 1 walks from Y0 to Y7.

1-to-8 demultiplexer truth table

S2 S1 S0	Output that gets D
000	Y0
001	Y1
010	Y2
011	Y3
100	Y4
101	Y5
110	Y6
111	Y7

With D = 0 every output is 0, whatever the select. Tie D to 1 and the same circuit is a 3-to-8 decoder; used the other way round, D works as an enable input.

You can also read the full theory in the lesson on encoders and demultiplexers. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

Build more parts from gates

half adder full adder half subtractor full subtractor 2:1 multiplexer 4:1 multiplexer XOR gate from NAND gates 2-to-4 decoder SR latch D flip-flop JK flip-flop T flip-flop 4-bit shift register 4-bit ripple carry adder D latch 1-to-4 demultiplexer 4-bit magnitude comparator 4-bit ring counter 4-bit Johnson counter 4-to-2 priority encoder 4-bit synchronous counter 3-to-8 decoder 8-to-1 multiplexer 4-bit carry lookahead adder half adder from NAND gates 2-bit comparator BCD to 7-segment decoder 4-bit up/down counter decade counter 2-bit multiplier 4-bit ALU 4-bit array multiplier NOT, AND, OR and NOR from NAND NOT, OR, AND and XOR from NOR full adder from NAND gates SR latch from NAND gates parity generator and checker 4-bit adder/subtractor BCD adder 4-bit universal shift register mod-6 counter 4-bit ripple counter binary to Gray code converter half adder from NOR gates full adder from NOR gates 4-bit register with parallel load 1011 sequence detector binary to BCD converter D flip-flop from NAND gates 1-bit ALU CMOS inverter CMOS NAND gate CMOS NOR gate PISO shift register SR flip-flop from NAND gates BCD to excess-3 code converter Hamming (7,4) code encoder and corrector traffic light controller 4-bit barrel shifter CMOS AND gate CMOS OR gate CMOS XOR gate 1-bit magnitude comparator half subtractor from NAND gates full subtractor from NAND gates 8-to-3 encoder Gray to binary converter 4-to-16 decoder full adder using 4:1 multiplexers edge detector serial adder 4-bit carry-select adder Mealy machine (1011 detector)master-slave JK flip-flop (NAND)half subtractor from NOR gates excess-3 to BCD code converter vending machine FSM 4-bit carry-save adder 3-bit synchronous counter (JK)CMOS transmission gate tri-state buffer (CMOS)2-to-1 mux from transmission gates mod-5 counter flip-flop conversion (JK to D)8-bit ALU decimal to BCD encoder BCD to decimal decoder 4-to-1 mux from 2-to-1 muxes

Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 1-to-8 demultiplexer in the lab →

Frequently asked

What is a 1 to 8 demultiplexer?

A circuit with one data input, three select inputs and eight outputs that routes the data input to the output numbered by the select value. All other outputs stay 0.

How many select lines does a 1-to-8 demultiplexer have?

Three, because 2 to the power 3 is 8. A 1-to-n demultiplexer needs log2(n) select lines.

What is a 1 to 2 demultiplexer?

The smallest demultiplexer: one select line S, with Y0 = D AND NOT S and Y1 = D AND S. It takes one NOT and two AND gates.

What is the difference between a demultiplexer and a decoder?

A decoder turns a number into one active line; a demultiplexer also has a data input that it steers to that line. A decoder with an enable input is the same circuit as a demultiplexer, with the enable as the data input.