7490 (74LS90): the decade counter chip, live

The 7490 (74LS90) is a decade counter chip: a divide-by-2 stage (QA, clocked by CKA) and a divide-by-5 stage (QB, QC, QD, clocked by CKB) that, with QA wired to CKB, count 0 to 9 in BCD on the falling edges of CKA. It also has two reset-to-zero inputs, R0(1) and R0(2), and two set-to-nine inputs, R9(1) and R9(2). This live circuit is wired for BCD.

TI's datasheet describes four master-slave flip-flops and gating "to provide a divide-by-two counter and a three-stage binary counter" whose cycle is divide-by-five, and explains how to get the full count: "the CKB input is connected to the QA output" and the count pulses go to CKA. That is how the live circuit is wired, so QD QC QB QA read the BCD count 0000 to 1001 and then wrap to 0000. The clock inputs act on the falling edge (the flip-flops in the datasheet's logic diagram have inverted clock inputs), so a count happens when CKA goes from 1 to 0. The resets are gated: both R0 inputs high clear the count, both R9 inputs high set it to 1001, and set-to-nine wins if both pairs are high; the datasheet mentions BCD nine's complement uses. Wire it the other way, QD into CKA and the pulses into CKB, and QA becomes a symmetrical divide-by-ten square wave. Here each stage is a master-slave D flip-flop with asynchronous set and clear (the A stage toggles, the B, C, D stages count 0 to 4 with DB = QB' QD', DC = QB XOR QC, DD = QB QC), clocked through inverters. Note the unusual power pins: VCC is pin 5 and GND pin 10. The live circuit opens held at zero (R0(1) = R0(2) = 1): set R0(1) to 0, then turn CKA on and off to count. Before the page is built, a 30-step sequence (reset, twelve counts through 9 and back, set to nine, one more count) is checked on all four outputs.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

4× D flip-flop with set and clear: QA (divide by 2) and QB, QC, QD (divide by 5)
1× NOR + 1 XOR + 1 AND: the divide-by-5 next state: DB = NOR(QB, QD), DC = QB XOR QC, DD = QB AND QC
3× AND + 1 NOT + 1 OR: the gated resets: R9 = R9(1) R9(2), R0 = R0(1) R0(2) NOT R9, and R0 OR R9 for QB and QC
2× NOT: falling-edge clocks for both stages (CKA, and QA as CKB)

Step by step

Place inputs CKA, R0(1), R0(2), R9(1), R9(2) and probes QA to QD.
Make QA a toggle flip-flop (D = NOT QA) clocked by NOT CKA, so it changes on CKA's falling edge.
Make QB, QC, QD a divide-by-5 counter clocked by NOT QA: DB = NOT (QB OR QD), DC = QB XOR QC, DD = QB AND QC. QA into this stage is the datasheet's CKB connection for BCD.
Add the resets: both R9 inputs high preset QA and QD and clear QB and QC (1001); both R0 inputs high, without R9, clear all four.
Release the resets and pulse CKA: the count steps 0, 1, 2, ..., 9 and back to 0.

BCD count sequence (QA wired to CKB)

Count	QD	QC	QB	QA
0	0	0	0	0
1	0	0	0	1
2	0	0	1	0
3	0	0	1	1
4	0	1	0	0
5	0	1	0	1
6	0	1	1	0
7	0	1	1	1
8	1	0	0	0
9	1	0	0	1

Reset inputs

R0(1)	R0(2)	R9(1)	R9(2)	Result
1	1	0	X	0000
1	1	X	0	0000
X	X	1	1	1001 (nine)
any other combination				count

7490 pinout

Pin	Name	Pin	Name
1	CKB	14	CKA
2	R0(1)	13	NC
3	R0(2)	12	QA
4	NC	11	QD
5	VCC	10	GND
6	R9(1)	9	QB
7	R9(2)	8	QC

X means the input does not matter. The count sequence, the reset table and the 14-pin pinout are from TI's SN74LS90 datasheet (SDLS940A), checked 2026-10-25. The same datasheet covers the 7492 (divide by 12) and 7493 (4-bit binary), which share the divide-by-2 stage. For a decade counter built the synchronous way, see the decade counter; for decoded outputs, the CD4017.

You can also read the full theory in the lesson on counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 74LS90 decade counter in the lab →

Frequently asked

How does the 7490 count to 10?

It has a divide-by-2 stage and a divide-by-5 stage. Connect QA to CKB and feed the pulses into CKA: QA toggles on every pulse, and every second pulse advances the divide-by-5 stage, so QD QC QB QA count 0 to 9 in BCD and wrap to 0.

Does the 7490 count on the rising or falling edge?

On the falling edge: the flip-flops in its logic diagram have inverted clock inputs, so the count advances when the clock goes from high to low.

What do R0 and R9 do on the 7490?

Both R0 inputs high reset the count to 0000. Both R9 inputs high set it to 1001 (nine), and this wins over R0. Each pair is ANDed, so you can tie one input of a pair high and control the other.

How do I make a divide-by-6 or divide-by-7 counter with a 7490?

Use the reset inputs: wire the outputs that are 1 at the count you want to skip to into R0(1) and R0(2). For divide by 6, QB and QC (count 6 = 0110) reset the counter as soon as it reaches 6.

Why are the 7490's power pins 5 and 10?

That is its pinout: VCC on pin 5 and GND on pin 10, unlike most 14-pin logic chips with VCC on 14 and GND on 7. Check it before wiring.