7474 (74LS74, 74HC74): the dual D flip-flop chip, live

The 7474 is a 14-pin chip with two independent positive-edge-triggered D flip-flops, each with an active-low preset (PRE) and clear (CLR): on a rising edge of CLK, Q takes the value of D, while PRE = 0 forces Q to 1 and CLR = 0 forces it to 0 at any time. The 74LS74 and 74HC74 share this pinout. This live chip has both flip-flops.

Each flip-flop here is built the way TI's SN74LS74A datasheet draws it: six 3-input NAND gates (each one an AND feeding a NAND in this simulator), three latches working together so that only the clock's rising edge can change Q. Preset and clear go straight into the NAND gates, which is why they act immediately, without waiting for the clock, and why holding both low at once forces Q and Q' both to 1, a state the datasheet calls nonstable because it does not survive releasing them. TI lists two uses that show what the chip is for: dividing a clock by 2 or 4 (wire Q' back to D and each flip-flop toggles on every edge, as in the frequency divider) and turning a momentary push button into an on/off toggle. Here CLK is a plain switch, so you clock the flip-flops by hand. The live chip opens with both flip-flops held clear (1CLR = 2CLR = 0): set CLR to 1, choose D, then turn CLK on to clock it in. Before the page is built, the flip-flop design is checked through 17 steps on its own (presets, clears, edges, holds and the nonstable state), and the chip through a 15-step sequence on all four outputs.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× D flip-flop with preset and clear: flip-flops 1 and 2, each from six 3-input NAND gates (six ANDs and six NANDs here)

Step by step

Place, for each flip-flop n, inputs nD, nCLK, nPRE and nCLR and probes nQ and nQbar.
Build each flip-flop from six 3-input NAND gates: two form the input latch that steers a set, two the latch that steers a reset, and two the output latch that holds Q and Q'.
Feed PRE into the set side and CLR into the reset side of all three latches, so either one acts at once.
Set CLR = 1 and PRE = 1, put a value on D, and turn CLK on: Q takes D on the rising edge and ignores D until the next one.

7474 function table (each flip-flop)

PRE	CLR	CLK	D	Q	Q'
0	1	X	X	1	0
1	0	X	X	0	1
0	0	X	X	1 (nonstable)	1 (nonstable)
1	1	rising	1	1	0
1	1	rising	0	0	1
1	1	0	X	no change	no change

7474 pinout

Pin	Name	Pin	Name
1	1CLR (active low)	14	VCC
2	1D	13	2CLR (active low)
3	1CLK	12	2D
4	1PRE (active low)	11	2CLK
5	1Q	10	2PRE (active low)
6	1Q'	9	2Q
7	GND	8	2Q'

X means the input does not matter. The function table and the 14-pin DIP and SOIC pinout are from TI's SN74HC74 (SCLS094F) and SN74LS74A (SDLS119) datasheets, checked 2026-10-25; the 74HC74 runs from 2 V to 6 V. For the flip-flop on its own, see the D flip-flop and how it differs from a latch in D latch vs D flip-flop.

You can also read the full theory in the lesson on the D flip-flop. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 7474 dual D flip-flop in the lab →

Frequently asked

What is a 7474?

A 14-pin chip with two independent D-type flip-flops, triggered by the rising edge of their clocks, each with active-low preset and clear inputs and both Q and Q' outputs. It is made as the 74LS74 (TTL) and the 74HC74 (CMOS), among others.

What do PRE and CLR do on the 7474?

They are asynchronous and active low. PRE = 0 sets Q to 1 and CLR = 0 resets it to 0 immediately, whatever the clock and D are doing. Keep both high for normal clocked operation.

What happens if PRE and CLR are both low?

Both Q and Q' go high. TI's datasheet calls this configuration nonstable: it does not persist when PRE or CLR returns high, so the final state is not guaranteed. Avoid releasing both at the same moment.

How do you make a divide-by-2 with a 7474?

Connect Q' to D and keep PRE and CLR high. Every rising clock edge loads the opposite of Q, so Q toggles and its frequency is half the clock's. Chain the second flip-flop from the first's Q to divide by 4.

What is the difference between the 74LS74 and the 74HC74?

The same two flip-flops and pinout. The 74LS74 is TTL for a 5 V supply; the 74HC74 is CMOS, runs from 2 V to 6 V and draws much less power.