D latch vs D flip-flop: the difference, live

A D latch is level-triggered: while its clock (enable) is 1 it is transparent and Q follows D, and when the clock is 0 it holds. A D flip-flop is edge-triggered: Q takes D only at the instant the clock rises, and holds it for the rest of the cycle. This live circuit feeds the same D and CLK into both, so you can watch the difference.

Set CLK to 1 and toggle D: the LATCH output follows every change, while FF does not move. Set CLK to 0 and both hold. Raise CLK again and FF copies whatever D is at that moment. The flip-flop here is built from two D latches with opposite enables (the master-slave design of the D flip-flop): the first is transparent while the clock is 0, the second while it is 1, so a value gets all the way through only at the rising edge. That is why registers and counters use flip-flops: with latches, a value could race through several stages during one long high phase, while edge triggering moves every stage exactly one step per clock. Latches are still useful where transparency is wanted, and they are smaller. Here CLK is a plain switch rather than a running clock, so you can hold it high as long as you like. Both outputs start out unknown until CLK first goes high, the way real ones power up in an unknown state. A 14-step sequence (D wiggled with CLK held high, then held low, then rising edges with D at 1 and at 0) is checked on both outputs before the page is built.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

1× D latch: D into its data input and CLK into its enable
1× D flip-flop: the same D and CLK; inside, two D latches with opposite enables

Step by step

Place inputs D and CLK and probes LATCH and FF.
Wire D to the data input of both parts, and CLK to the latch's enable and the flip-flop's clock.
Set CLK = 1 so both outputs become defined, then toggle D: LATCH follows each change and FF stays put.
Set CLK = 0 and toggle D: now both hold their values.
Raise CLK again: FF takes the value D has at that instant, and LATCH starts following D again.

The checked sequence, step by step

Step	D	CLK	LATCH	FF	What happens
1	0	0 to 1	0	0	First rising edge: both take D = 0
2	1	1	1	0	CLK high: the latch follows D, the flip-flop does not
3	0	1	0	0	The latch follows again
4	1	1	1	0	And again
5	1	1 to 0	1	0	CLK falls: both hold
6	0	0	1	0	D changes, nothing else does
7	1	0 to 1	1	1	Rising edge with D = 1: the flip-flop updates
8	0	1	0	1	The latch follows D, the flip-flop holds its 1
9	0	1 to 0	0	1	Both hold
10	0	0 to 1	0	0	Rising edge with D = 0

The rows summarize the 14 checked steps (a few repeat a step with D toggled while CLK is 0). The flip-flop changes only in the rows where CLK goes from 0 to 1; the latch changes whenever D does while CLK is 1. More in the lessons on the D latch and the D flip-flop.

You can also read the full theory in the lesson on why a latch is not enough. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the D latch vs D flip-flop in the lab →

Frequently asked

What is the difference between a D latch and a D flip-flop?

A D latch is level-triggered: while its enable is 1, Q follows D continuously. A D flip-flop is edge-triggered: Q changes only at the clock's rising (or falling) edge, taking the value D has at that instant, and ignores D the rest of the time.

What does transparent mean for a latch?

While the enable is active, a latch passes D straight through to Q, as if it were a wire, so every change on D appears on Q. When the enable goes inactive it stops passing and holds the last value.

Why do registers use flip-flops instead of latches?

Because in a chain of storage elements on one clock, transparent latches would let a value run through several stages during a single high phase. Flip-flops sample only at the edge, so every stage moves exactly one step per clock.

Is a flip-flop made of latches?

Often, yes. A master-slave D flip-flop is two D latches in series with opposite enables: the master is transparent while the clock is low, the slave while it is high, so D reaches Q only at the rising edge.

Which is faster, a latch or a flip-flop?

A latch is smaller and passes data with less delay, since it is half of a master-slave flip-flop. Flip-flops are easier to design with, because their outputs change only at clock edges.