74HC595 shift register: how it works, live

The 74HC595 is an 8-bit serial-in, parallel-out shift register with an output latch: each rising edge on SRCLK shifts the bit on SER into the first of eight stages, and a rising edge on RCLK copies all eight stages at once to the outputs QA to QH. That second register is why the outputs do not flicker while new data shifts in, and why three wires can drive eight outputs.

TI's datasheet describes it as "an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register" with 3-state outputs and separate clocks for the two registers. This live circuit has exactly those parts: eight D flip-flops with clear for the shift register, eight more for the storage register, and eight tri-state buffers, built from transistors, on the outputs. SRCLR, active low, clears the shift register at once (the storage register keeps its value until the next RCLK). OE, also active low, disconnects QA to QH, which then float. QH' is the last shift stage, always connected: wire it to SER of a second 74HC595 and the two act as one 16-bit register, which is how a microcontroller drives long chains of LEDs from three pins (data, shift clock and latch clock). Both clocks trigger on the rising edge, and the datasheet notes that if you tie them together the shift register stays one clock pulse ahead of the storage register. The live circuit opens with SRCLR low, holding the shift register clear: set SRCLR to 1, then for each bit set SER and pulse SRCLK, and pulse RCLK to show the result. QA to QH read as unknown until the first RCLK pulse, as on a powered-up chip. Before the page is built, a 39-step sequence (clear, shift in 10110010, latch, shift again with the outputs holding, disable and re-enable the outputs, latch, clear and latch) is checked on all nine outputs.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

8× D flip-flop with clear: the shift register, clocked by SRCLK and cleared by NOT SRCLR
8× D flip-flop: the storage register, clocked by RCLK
8× tri-state buffer: the outputs QA to QH, enabled by NOT OE (each one 8 transistors)
2× NOT: the active-low SRCLR and OE

Step by step

Place inputs SER, SRCLK, SRCLR, RCLK and OE, and probes QA to QH and QH'.
Chain eight D flip-flops with clear into a shift register: SER into the first, each Q into the next D, all clocked by SRCLK and cleared by NOT SRCLR. The last Q is QH'.
Give each stage a storage flip-flop clocked by RCLK, so the outputs change only when RCLK rises.
Put a tri-state buffer on each storage output, enabled by NOT OE, and probe the buffers as QA to QH.
Set SRCLR = 1, shift in 1, 0, 1, 1, 0, 0, 1, 0 (set SER, pulse SRCLK) and pulse RCLK: the first bit sent ends up on QH and the last on QA.

74HC595 function table

SER	SRCLK	SRCLR	RCLK	OE	What happens
X	X	X	X	1	QA to QH are disabled (high impedance)
X	X	X	X	0	QA to QH are enabled
X	X	0	X	X	The shift register is cleared
0	rising	1	X	X	The first stage takes 0, every other stage takes the one before it
1	rising	1	X	X	The first stage takes 1, every other stage takes the one before it
X	X	X	rising	X	The shift register's contents are copied to the storage register

74HC595 pinout

Pin	Name	Pin	Name
1	QB	9	QH' (serial out)
2	QC	10	SRCLR (active low)
3	QD	11	SRCLK
4	QE	12	RCLK
5	QF	13	OE (active low)
6	QG	14	SER
7	QH	15	QA
8	GND	16	VCC

X means the input does not matter. The function table and the 16-pin pinout (SOIC, PDIP, SSOP and TSSOP) are from TI's SN74HC595 datasheet (SCLS041J), checked 2026-10-25; it runs from 2 V to 6 V. Note that QA is on pin 15, across the chip from QB to QH on pins 1 to 7. For the opposite job, reading eight inputs over a few wires, see the 74HC165 and the PISO shift register.

You can also read the full theory in the lesson on shift registers. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 74HC595 shift register in the lab →

Frequently asked

How does the 74HC595 work?

It has two 8-bit registers. A rising edge on SRCLK shifts the bit on SER into the shift register, moving every stored bit along by one. A rising edge on RCLK copies the whole shift register into the storage register that drives the outputs QA to QH, so the outputs change all at once.

What is the difference between SRCLK and RCLK?

SRCLK is the shift clock: each rising edge moves the data one stage along. RCLK is the storage (latch) clock: its rising edge transfers the eight shifted bits to the outputs. Keeping them separate lets you shift a new byte in without the outputs flickering.

How do you chain two 74HC595s?

Connect QH' (pin 9) of the first chip to SER (pin 14) of the second, and share SRCLK, RCLK, SRCLR and OE. Shift 16 bits in and pulse RCLK once: the first eight bits sent end up in the second chip.

What do OE and SRCLR do?

Both are active low. OE high puts the outputs QA to QH in the high-impedance state; tie it low to keep them on. SRCLR low clears the shift register immediately (not the storage register); tie it high in normal use.

Which output gets the first bit shifted in?

After eight shifts the first bit you sent sits in the last stage, QH, and the last bit you sent is in QA. That is why code that drives a 74HC595 sends the most significant bit first when QH is meant to be bit 7.