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How a Wallace tree multiplier works: 4 x 4 bits, live

A Wallace tree multiplier adds the partial products of a binary multiplication in layers of full and half adders that work in parallel, reducing every column to at most two bits, and only then uses one ordinary adder to finish. This live 4 x 4 one needs 16 AND gates, two reduction layers and a final ripple adder: 7 full adders and 8 half adders in all.

Multiplying two 4-bit numbers makes 16 partial-product bits, a_i AND b_j, each worth 2^(i+j). Lined up by weight they form columns of 1, 2, 3, 4, 3, 2 and 1 bits. An array multiplier adds them row after row, so its delay grows with the number of rows. A Wallace tree instead uses full adders as 3-to-2 counters: three bits of one column become a sum bit in that column and a carry bit in the next, and nothing waits for a carry to ripple. Each layer takes every three bits of a column into a full adder and a leftover pair into a half adder, which cuts the height by about a third, so n rows need only about log base 3/2 of n layers. Chris Wallace proposed it in 1964. The adders here are the half adder and full adder saved as parts, the same way the carry-save adder adds three numbers at once. All 256 products are checked before the page is built.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

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What you need

Step by step

  1. Place inputs A3 to A0 and B3 to B0, and probes P7 to P0.
  2. Make the 16 partial products a_i AND b_j and sort them into columns by weight i + j.
  3. Layer 1: in every column, send each group of three bits into a full adder and a leftover pair into a half adder; sums stay in the column, carries move one column left.
  4. Layer 2: repeat on the new columns until none holds more than two bits.
  5. Add the final two rows with a short ripple adder. Try 1111 x 1111: P = 1110 0001, which is 225.

Worked examples

ABDecimalP (8 bits)
001101013 x 5 = 1500001111
011001116 x 7 = 4200101010
100110109 x 10 = 9001011010
1101101113 x 11 = 14310001111
1111111115 x 15 = 22511100001

The reduction layers have no carry chain at all, so their delay is two full-adder delays whatever the numbers are; only the final adder carries. For wider multipliers the gap grows: 16 rows need 6 Wallace layers, where an array multiplier passes through about 15 rows of adders.

You can also read the full theory in the lesson on binary multiplication in hardware. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 4x4 Wallace tree multiplier in the lab →

Frequently asked

What is a Wallace tree multiplier?

A hardware multiplier that adds the partial products in parallel layers of full and half adders, each acting as a counter that turns three bits of a column into a sum and a carry, until two rows remain, and then adds those two rows with a fast adder.

Why is a Wallace tree faster than an array multiplier?

An array multiplier adds the partial products one row at a time, so its delay grows linearly with the width. A Wallace tree reduces all columns at once and cuts the number of rows by about a third per layer, so the reduction takes a logarithmic number of layers, and only the final addition has a carry chain.

How many full adders does a 4x4 Wallace tree need?

This one uses 7 full adders and 8 half adders, counting the final ripple adder, plus 16 AND gates for the partial products. Variants differ slightly in how they place half adders.

What is the difference between Wallace and Dadda multipliers?

Both reduce partial products with full and half adders. Wallace reduces as much as possible in every layer, while Dadda reduces only as much as needed to reach the next target height, which uses fewer half adders at the cost of a slightly wider final adder.