74LS138 decoder: how the 3-to-8 line decoder chip works
The 74LS138 (and its CMOS version, the 74HC138) is a 3-to-8 line decoder chip: the select inputs C B A pick one of the eight outputs Y0 to Y7, and that output goes LOW while the other seven stay HIGH. It decodes only while all three enables agree, G1 = 1 and G2A = G2B = 0; otherwise every output is HIGH.
This live circuit is the chip's logic, gate for gate, taken from the logic diagram in Texas Instruments' datasheet: the enable is G1 AND NOT (G2A OR G2B), the select bits are decoded into eight lines, and each output is a NAND of its line with the enable, which is what makes the outputs active low. Active-low outputs suit their main job, picking one memory or I/O chip out of eight, because chip-select inputs are usually active low too. The three enables are what make the '138 easy to grow: TI's datasheet notes that a 24-line decoder needs no external inverters and a 32-line decoder only one. Two of them make a 4-to-16 decoder: drive G2A of the first and G1 of the second with the top address bit D. It is also a 1-to-8 demultiplexer: hold G1 = 1 and G2B = 0, feed the data into G2A, and the selected output follows it. The live circuit opens with G1 = 1 and everything else 0, so Y0 is LOW. All 64 input combinations are checked against the datasheet's function table before the page is built. The plain version without enables or inversion is the 3-to-8 decoder.
Open this circuit in the lab →
What you need
- 1× NOR: NOT (G2A OR G2B): both active-low enables must be LOW
- 1× AND: the enable EN = G1 AND NOR(G2A, G2B)
- 3× NOT: NOT C, NOT B and NOT A
- 4× AND: the four B A combinations, shared by both halves
- 8× AND: each B A line combined with C or NOT C: one line per output
- 8× NAND: Yk = NAND(line k, EN), LOW only for the selected line while enabled
Step by step
- Place the enables
G1,G2A,G2B, the select inputsC,B,A(C is the most significant bit) and probesY0toY7. - Build the enable:
EN = G1 AND NOR(G2A, G2B). It is 1 only for G1 = 1, G2A = 0 and G2B = 0. - Decode C B A into eight lines exactly as in the 3-to-8 decoder: three NOTs, four ANDs for B A, eight ANDs with C or NOT C.
- NAND each line with EN for the outputs. A NAND is LOW only when both inputs are 1, so only the selected output goes LOW, and only while the chip is enabled.
- Set G1 = 1 and count C B A from 000 to 111: the single LOW output steps from Y0 to Y7. Now set G2A = 1 and every output goes HIGH.
74LS138 truth table (function table)
| G1 | G2A | G2B | C | B | A | Y0 | Y1 | Y2 | Y3 | Y4 | Y5 | Y6 | Y7 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| X | 1 | X | X | X | X | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| X | X | 1 | X | X | X | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| 0 | X | X | X | X | X | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 |
| 1 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
74LS138 pinout
| Pin | Name | Function |
|---|---|---|
| 1 | A | Select input, least significant bit |
| 2 | B | Select input |
| 3 | C | Select input, most significant bit |
| 4 | G2A | Enable, active LOW |
| 5 | G2B | Enable, active LOW |
| 6 | G1 | Enable, active HIGH |
| 7 | Y7 | Output 7, active LOW |
| 8 | GND | Ground |
| 9 to 15 | Y6 to Y0 | Outputs 6 down to 0 (pin 9 is Y6, pin 15 is Y0), active LOW |
| 16 | VCC | Supply, +5 V for the 74LS138 |
X means the input does not matter: any one disabling enable forces all eight outputs HIGH. Pin numbers are for the 16-pin DIP and SOIC packages, from the TI datasheets for the SN74LS138 (SDLS014) and SN74HC138 (SCLS107G), checked 2026-10-25; the LS and HC parts share the pinout and function table, while the HC part runs from 2 V to 6 V.
You can also read the full theory in the lesson on decoders. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.
Build more parts from gates
Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.
Open the 74LS138 decoder in the lab →Frequently asked
What does the 74LS138 do?
It is a 3-to-8 line decoder and demultiplexer. The 3-bit select input C B A chooses one of eight outputs, Y0 to Y7, and drives it LOW; the other outputs stay HIGH. Three enable inputs (G1 active high, G2A and G2B active low) must all be active, otherwise every output is HIGH.
Why are the 74LS138 outputs active low?
Each output is a NAND gate, which is faster and cheaper than AND in TTL and CMOS, and the chips it usually selects (memories, peripherals) have active-low chip-select inputs. So a LOW output means "selected".
What is the difference between the 74LS138 and the 74HC138?
The logic, function table and pinout are the same. The 74LS138 is a bipolar TTL (low-power Schottky) part for 5 V supplies; the 74HC138 is high-speed CMOS, runs from 2 V to 6 V and draws far less supply current when idle.
How do you make a 4-to-16 decoder from two 74LS138s?
Connect A, B and C to both chips and use the fourth address bit D as an enable: wire D to G2A of the first chip (enabled when D = 0, outputs 0 to 7) and to G1 of the second (enabled when D = 1, outputs 8 to 15). Tie the remaining enables active.
How is the 74LS138 used as a demultiplexer?
Hold G1 = 1 and G2B = 0 and feed the data into G2A. C B A choose the output: the selected output copies the data (LOW when the data is LOW), and the others stay HIGH.