How to build a frequency divider: divide a clock by 2, 4 and 3

A frequency divider, or clock divider, turns a clock into a slower one. A D flip-flop that feeds its own Q' back to D toggles on every clock edge, so its output runs at half the clock frequency; a second toggle stage clocked by the first divides by 4; and a mod-3 counter divides by 3. This live circuit has all three, side by side, driven by one CLK.

Each toggle stage halves the frequency, so a chain of n stages divides by 2 to the n: that chain is exactly a ripple counter, read one output at a time. To divide by a number that is not a power of two, use a counter that wraps after N states and take one of its bits: here a two-flip-flop counter steps 00, 01, 10 and back, and its top bit is high for one clock in three. That output has a one-third duty cycle; a 50% duty cycle for an odd divisor needs a second set of flip-flops on the falling edge, combined with the first. Larger divisors work the same way, as in the mod-5 counter and the decade counter (divide by 10). Microcontrollers use dividers like these, often called prescalers, to run timers and serial ports at a fraction of the main clock. Every output is checked at the end of each of 24 clock cycles before the page is built.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

2× D flip-flop with clear: toggle stages: D = Q', the first clocked by CLK (DIV2), the second by the first's Q' (DIV4)
2× D flip-flop with clear: the mod-3 counter, both clocked by CLK (DIV3 is its top bit)
1× NOR: D0 = NOR(Q1, Q0), so the counter goes 00, 01, 10, 00

Step by step

Place a clock CLK, an input CLR, and probes DIV2, DIV4 and DIV3.
Divide by 2: a D flip-flop clocked by CLK with its Q' wired back to D. Its Q is DIV2.
Divide by 4: a second toggle flip-flop clocked by the first one's Q', so it flips each time DIV2 falls. Its Q is DIV4.
Divide by 3: two flip-flops on CLK with D0 = NOR(Q1, Q0) and D1 = Q0. Q1 is DIV3.
Wire CLR to every flip-flop's clear, pulse it once, then run the clock: DIV2 flips every edge, DIV4 every second edge, DIV3 is high one edge in three.

Outputs after each clock edge

Edges since CLR	DIV2	DIV4	DIV3
0	0	0	0
1	1	0	0
2	0	1	1
3	1	1	0
4	0	0	0
5	1	0	1
6	0	1	0
7	1	1	0
8	0	0	1
9	1	0	0
10	0	1	0
11	1	1	1

DIV2 repeats every 2 clock edges, DIV4 every 4 and DIV3 every 3, so with a 12 MHz clock they would run at 6, 3 and 4 MHz. Because each toggle stage waits for the one before it, DIV4 changes a little after DIV2 in real hardware; when that skew matters, clock every stage from CLK as in a synchronous counter.

You can also read the full theory in the lesson on counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the frequency divider (by 2, 4 and 3) in the lab →

Frequently asked

What is a frequency divider?

A circuit whose output clock runs at an exact fraction of its input clock: 1/2, 1/4, 1/3 and so on. In digital logic it is built from flip-flops, as a toggle stage for divide by 2 or as a counter that wraps after N states for divide by N.

How do you divide a clock frequency by 2?

Use one D flip-flop with its Q' output wired back to its D input. On every clock edge it stores the opposite of its current state, so it toggles once per clock period and its output has half the frequency, with a 50% duty cycle.

How do you divide a clock by 3?

Build a counter with three states, such as two flip-flops that go 00, 01, 10 and back, and use one of its bits as the output. Here D0 = NOR(Q1, Q0) and D1 = Q0, and Q1 is high for one clock in three. For a 50% duty cycle, add flip-flops on the falling clock edge and combine their output with the rising-edge one.

Is a frequency divider the same as a counter?

Essentially yes: every counter is a frequency divider, since its lowest bit runs at half the clock, the next at a quarter, and its wrap-around repeats once every N clocks. A divider is a counter used for its timing rather than its count.

What is a clock prescaler?

A frequency divider in front of a timer or peripheral, usually with a selectable ratio such as 1, 8, 64 or 256, so the peripheral can count slowly without slowing the main clock.