How to build a 3-bit Gray code counter

A Gray code counter steps through 000, 001, 011, 010, 110, 111, 101, 100 and back to 000, so exactly one bit changes on every clock. This live one uses three D flip-flops and next-state logic read off K-maps: D2 = Q1 Q0' + Q2 Q0, D1 = Q2' Q0 + Q1 Q0' and D0 = Q2 XNOR Q1.

A binary counter can change several bits at once, as when 011 becomes 100, and in real hardware those bits never switch at exactly the same moment, so anything reading the count mid-change can see a value that was never there. A Gray code counter changes one bit per step, so a reading is always either the old value or the new one. That is why the read and write pointers of an asynchronous FIFO, which cross between two clock domains, are usually kept in Gray code, and why rotary encoders use it. The design is the standard one for any synchronous state machine: list each state and its successor, make a K-map for each next-state bit, and wire the minimized equations into the D inputs. The other way to build one is a binary counter followed by a binary to Gray converter, which costs two XOR gates but loses the one-bit-change guarantee at the converter's inputs. Two full laps of the eight codes are checked, every output at the end of every cycle, before the page is built.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

3× D flip-flop with clear: the state bits G2, G1, G0, all clocked by CLK
2× AND + 1 OR: D2 = Q1 Q0' + Q2 Q0
2× AND + 1 OR: D1 = Q2' Q0 + Q1 Q0'
1× XNOR: D0 = Q2 XNOR Q1

Step by step

Place a clock CLK, an input CLR, three D flip-flops with clear, and probes G2, G1 and G0 on their Q outputs.
Write the state table: 000 goes to 001, 001 to 011, 011 to 010, 010 to 110, 110 to 111, 111 to 101, 101 to 100 and 100 back to 000.
Minimize each next-state bit with a K-map and wire it: D2 = Q1 Q0' + Q2 Q0, D1 = Q2' Q0 + Q1 Q0', D0 = Q2 XNOR Q1.
Connect CLK and CLR to all three flip-flops, pulse CLR, then run the clock and watch one output change per edge.

The count, edge by edge

Edges since CLR	G2 G1 G0	Bit that changed
0	0 0 0	(start)
1	0 0 1	G0
2	0 1 1	G1
3	0 1 0	G0
4	1 1 0	G2
5	1 1 1	G0
6	1 0 1	G1
7	1 0 0	G0
8	0 0 0	G2

Every row differs from the one before in exactly one bit, including the wrap from 100 back to 000. Read as binary the sequence is 0, 1, 3, 2, 6, 7, 5, 4; the Gray code converter turns any code back into its count.

You can also read the full theory in the lesson on Gray code. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 3-bit Gray code counter in the lab →

Frequently asked

What is a Gray code counter?

A counter whose output follows the Gray code sequence, in which consecutive values differ in exactly one bit, instead of ordinary binary. A 3-bit one counts 000, 001, 011, 010, 110, 111, 101, 100 and repeats.

Why use a Gray code counter?

Because only one bit changes per step, a reader that samples the count while it is changing gets either the old or the new value, never a mixture. This makes Gray counters the usual choice for FIFO pointers that cross clock domains, and it also avoids decoding glitches.

How do you design a Gray code counter?

Treat it as a state machine: write each state and its next state, draw a K-map for each next-state bit, and use the minimized equations as the D inputs of the flip-flops. For 3 bits that gives D2 = Q1 Q0' + Q2 Q0, D1 = Q2' Q0 + Q1 Q0' and D0 = Q2 XNOR Q1.

Can I make a Gray counter from a binary counter?

Yes: feed a binary counter's outputs through a binary to Gray converter, where G_i = B_i XOR B_(i+1) and the top bit passes straight through. It is simpler to design, but the converter's inputs still change several bits at once, so the output can glitch briefly between steps.