AOI gate: an AND-OR-INVERT gate in 6 transistors

An AOI (AND-OR-INVERT) gate computes NOT (A B + C) in a single CMOS stage. This AOI21 uses only 6 transistors: the NMOS pull-down network is A and B in series, in parallel with C, and the PMOS pull-up network is its dual, A and B in parallel, in series with C.

Static CMOS gates are naturally inverting, so any function written as NOT of a sum of products fits in one gate: each AND becomes transistors in series in the pull-down network, each OR becomes transistors in parallel, and the pull-up network is the same picture with series and parallel swapped. Built from separate gates, NOT (A B + C) would be an AND (a NAND plus an inverter, 6 transistors) followed by a NOR (4 more), 10 transistors in two stages; the AOI does it in 6 and one stage, which is why standard-cell libraries offer AOI and OAI cells. The name counts the inputs of each AND: AOI21 has one 2-input AND and one single input, while AOI22 is NOT (A B + C D) in 8 transistors. The mirror image is the OAI (OR-AND-INVERT) gate, NOT ((A + B) C), whose pull-down is A parallel B, in series with C. On every input row exactly one of the two networks conducts, so Y is always driven; all 8 rows are checked on the transistor circuit before the page is built. Compare the simpler CMOS NAND and CMOS NOR.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

3× NMOS: the pull-down network: A and B in series, with C in parallel to the pair
3× PMOS: the pull-up network: A and B in parallel, in series with C

Step by step

Place a VDD rail, a GND rail, inputs A, B and C, and a probe Y.
Build the pull-down network from the expression inside the NOT, A B + C: NMOS A and NMOS B in series from Y to GND for the AND, and NMOS C from Y to GND in parallel with them for the OR.
Build the pull-up network as its dual: PMOS A and PMOS B in parallel from VDD to a middle node, then PMOS C in series from that node to Y.
Drive each transistor's gate from its input, then step through all eight rows: Y is 0 whenever A and B are both 1 or C is 1.

AOI21 truth table

A	B	C	A B + C	Y
0	0	0	0	1
0	0	1	1	0
0	1	0	0	1
0	1	1	1	0
1	0	0	0	1
1	0	1	1	0
1	1	0	1	0
1	1	1	1	0

Y is 1 on three rows only: C = 0 and at least one of A and B is 0. Those are exactly the rows where the pull-up path is closed (C's PMOS on, plus A's or B's) and the pull-down is open.

You can also read the full theory in the lesson on designing CMOS gates from truth tables. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the CMOS AOI gate (AOI21) in the lab →

Frequently asked

What is an AOI gate?

An AND-OR-INVERT gate: it ANDs some inputs, ORs the results and inverts, all in one CMOS stage. The AOI21 computes Y = NOT (A B + C).

How many transistors are in an AOI21 gate?

Six: three NMOS in the pull-down network and three PMOS in the pull-up network, one of each per input. An AOI22, NOT (A B + C D), needs eight.

What is the difference between AOI and OAI gates?

They are duals. An AOI gate is NOT (A B + C): ANDs first, then OR. An OAI (OR-AND-INVERT) gate is NOT ((A + B) C): ORs first, then AND. In an OAI21 the pull-down is A parallel B, in series with C, and the pull-up is A series B, in parallel with C.

Why use AOI gates?

Because static CMOS gates invert for free, an AND-OR-INVERT function fits in one stage with one transistor pair per input. Making it from separate AND, OR and NOT gates takes more transistors and more stages, so it is bigger and slower.

How do you design the pull-up network of a CMOS gate?

Write the pull-down network from the expression inside the NOT (AND as series, OR as parallel), then take its dual: swap every series connection for parallel and every parallel one for series, using PMOS transistors. Exactly one network then conducts for every input combination.