74HC161 (74LS161): the synchronous 4-bit counter, live

The 74HC161 is a synchronous 4-bit binary counter: on each rising edge of CLK it adds 1 to QD QC QB QA while ENP and ENT are both high, loads the inputs D C B A instead when LOAD is low, and clears to 0000 at once when CLR goes low. RCO (ripple carry out) is high at 15 so counters can be chained. This live circuit behaves like the chip.

TI's datasheet calls it a synchronous, presettable counter with internal carry look-ahead: all four flip-flops are clocked together, which "eliminates the output counting spikes" of ripple counters (compare the ripple counter). Bit i flips on a clock edge when ENP, ENT and all the bits below it are 1, the same rule as the synchronous counter; this version gets each D input from an XOR of the bit with that condition, then a 2-to-1 choice between the count and the load data. The datasheet is careful about which controls wait for the clock: LOAD is synchronous ("the outputs agree with the setup data after the next clock pulse"), but CLR is asynchronous ("a low level at the clear (CLR) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs"). ENT also gates RCO, so a chain of counters is built by feeding each RCO into the next counter's ENT. Here CLK is a plain switch. The live circuit opens held clear (CLR = 0) with ENP, ENT and LOAD high: set CLR to 1 and pulse CLK to count. Before the page is built, a 61-step sequence (17 counts through 15 and back to 0, holds with ENP and with ENT low, a synchronous load of 1010, more counts and an asynchronous clear) is checked on all five outputs.

Big circuit: pinch, scroll or tap + to zoom in, then drag to move around.

Live circuit: click the inputs to toggle them and watch the outputs update. It runs the real simulator, right here on the page.

Open this circuit in the lab →

What you need

4× D flip-flop with clear: QA to QD, all on CLK, cleared by NOT CLR
1× AND + 3 AND: the count enable ENP AND ENT, and the toggle conditions for QB, QC and QD
4× XOR: each bit XOR its toggle condition, the next count
8× AND + 4 OR: the 2-to-1 choice per bit: count when LOAD = 1, input data when LOAD = 0
4× AND: RCO = ENT AND QA AND QB AND QC AND QD
2× NOT: the active-low CLR and LOAD

Step by step

Place inputs CLR, CLK, A to D, ENP, ENT and LOAD, and probes QA to QD and RCO.
Put four D flip-flops with clear on one CLK, cleared by NOT CLR, so the clear does not wait for the clock.
Compute the next count: bit i toggles when ENP AND ENT AND all lower bits are 1, so its next value is Qi XOR that condition.
Before each D input, choose the next count when LOAD = 1 or the input A to D when LOAD = 0.
Add RCO = ENT QA QB QC QD. Set CLR to 1 and pulse CLK: the count runs 0 to 15, RCO lights at 15, and the next pulse wraps to 0.

74HC161 function summary

CLR	LOAD	ENP	ENT	CLK	What happens
0	X	X	X	X	Clear to 0000 at once (asynchronous)
1	0	X	X	rising	Load D C B A (synchronous)
1	1	1	1	rising	Count up by 1
1	1	0	X	rising	Hold
1	1	X	0	rising	Hold, and RCO is 0

74HC161 pinout

Pin	Name	Pin	Name
1	CLR (active low)	16	VCC
2	CLK	15	RCO
3	A	14	QA
4	B	13	QB
5	C	12	QC
6	D	11	QD
7	ENP	10	ENT
8	GND	9	LOAD (active low)

X means the input does not matter. QA is the least significant bit. The behavior and the 16-pin pinout are from TI's SN74HC161 datasheet (SCLS297D), checked 2026-10-25; it runs from 2 V to 6 V. The datasheet also notes that changes on ENP, ENT or LOAD do nothing until the next clock edge.

You can also read the full theory in the lesson on synchronous counters. Prefer to build it yourself from scratch? Open the digiwleea lab and place the gates on the canvas, or start from the logic gate simulator.

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Each of these is one step from a transistor to a working CPU. Build every gate from CMOS transistors and work all the way up in the free digiwleea lab, with the free theory reference alongside.

Open the 74HC161 4-bit counter in the lab →

Frequently asked

What does the 74HC161 do?

It is a 4-bit synchronous binary counter. On each rising clock edge it counts up when ENP and ENT are high, loads a new value from inputs A to D when LOAD is low, and it can be cleared to zero at any time by taking CLR low.

Is the 74HC161 clear synchronous or asynchronous?

Asynchronous: a low level on CLR sets all four outputs low immediately, regardless of the clock, LOAD or the enable inputs. Its load, by contrast, is synchronous and waits for the next clock edge.

What is the difference between ENP and ENT?

Both must be high to count. ENT also enables the ripple carry output RCO, so when chaining counters you feed each RCO into the next counter's ENT and use ENP as a common enable.

How do you make a mod-10 counter with a 74HC161?

Load 0000 when the count reaches 9: with A to D at 0, drive LOAD low whenever QD and QA are both 1 (a NAND gate of QD and QA does it, since 1001 is the first count with both set), so the next clock edge loads 0 instead of counting to 10. Because the load is synchronous, the count shows 9 for a full clock period.

What is the difference between the 74LS161 and the 74HC161?

The same counter and pinout in different technologies: the 74LS161 is TTL for 5 V, the 74HC161 is CMOS for 2 V to 6 V with lower power.